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1. About the F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide
2. About this IP
3. Getting Started
4. F-Tile Low Latency 50G Ethernet Intel® FPGA IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. Document Revision History for the F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide
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8.2. RX MAC Registers
Addr | Name | Description | Reset | Access |
---|---|---|---|---|
0x500 | RXMAC_REVID | RX MAC revision ID for 50G Ethernet IP core. |
0x0916 2016 | RO |
0x501 | RXMAC_SCRATCH | Scratch register available for testing. | 0x0000 0000 | RW |
0x502 | RXMAC_NAME_0 | First 4 characters of IP core variation identifier string, "50gMACRxCSR". |
0x3235 674D | RO |
0x503 | RXMAC_NAME_1 | Next 4 characters of IP core variation identifier string, "ACRx". | 0x4143 5278 | RO |
0x504 | RXMAC_NAME_2 | Final 4 characters of IP core variation identifier string, "0CSR". The "0" is unprintable. | 0x0043 5352 | RO |
0x506 | MAX_RX_SIZE_CONFIG | Specifies the maximum frame length available. The MAC asserts l1_rx_error[3] when the length of the received frame exceeds the value of this register. If the IP core receives an Ethernet frame of size greater than the number of bytes specified in this register, and the IP core includes statistics registers, the IP core increments the 64-bit CNTR_RX_OVERSIZE counter. |
0xXXXX 2580 3 | RW |
0x507 | MAC_CRC_CONFIG | The RX CRC forwarding configuration register. The following encodings are defined:
|
31'hX1'b0 3 | RW |
0x508 | LINK_FAULT | Link Fault Status Register.
If you turn on Enable link fault generation, the following bit fields are defined:
If you disable Enable link fault generation, bit[0] and [1] are always zero. |
30'hX2'b00 3 | RO |
0x50A | RXMAC_CONTROL | RX MAC Control Register. A single bit is defined:
|
27'hX_5'b0XX0X 3 | RW |
3 X means "Don't Care".