F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide

ID 758946
Date 1/09/2024

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Document Table of Contents

2. About this IP

The F-Tile Low Latency 50G Ethernet implements the 25G & 50G Ethernet Specification, Draft 1.6 from the 25 Gigabit Ethernet Consortium and the IEEE 802.3by 25Gb Ethernet specification. The IP includes an option to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard. The media access control (MAC) client side interface for the F-Tile Low Latency 50G Ethernet is a 64-bit Avalon® streaming interface. It maps to two 25.78125 Gbps transceivers. Transceiver interface to 25GBASE-SR optical Physical Medium Dependent (PMD) transceiver is supported.

The F-Tile Low Latency 50G Ethernet Intel® FPGA IP provides standard media access control (MAC) and physical coding sublayer (PCS), Reed-Solomon Forward Error Correction (RS-FEC), and physical medium attachment (PMA) functions shown in the following block diagrams. The physical layer (PHY) comprises the PCS, optional RS-FEC, and elective PMA.

Figure 1.  F-Tile Low Latency 50G Ethernet MAC, PCS, and PMA IP Block Diagram

The following block diagram shows an example of a network application with F-Tile Low Latency 50G Ethernet MAC and PHY.

Figure 2. Example Network Application