F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide

ID 758946
Date 1/09/2024
Public

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7.8. Clock Signals

The F-Tile Reference and System PLL Clocks Intel® FPGA IP is required to generate i_clk_ref and i_clk_sys input clocks that drive this IP core.

A 390.625 MHz transmit clock (clk_txmac) is derived from Tx clock divider of Ethernet_F-Tile IP. This clock is guaranteed stable when tx_lanes_stable is high.

A 390.625 MHz receive clock (clk_rxmac) is derived from Rx clock divider of eth_f IP. This clock is guaranteed stable when rx_pcs_ready is high.

The Avalon® MM clock (clk_status) is nominally 100 MHz but can be as high as 125 MHz.

Table 18.  Clock Signals
Signal Name Direction Width Nominal Frequency Description
i_clk_ref Input 1  

156.25 MHz transceiver reference clock. You must specify this frequency in the F-Tile Reference and System PLL Clock Intel® FPGA IP FGT refclk frequency IP parameter.

Connect this signal to the out_refclk_fgt_<i> output signal of the F-Tile Reference and System PLL Clocks Intel® FPGA IP.

i_clk_sys Input 1  

805.6640625 MHz Ethernet system clock. You must specify this frequency in the F-Tile Reference and System PLL Clock Intel® FPGA IP Mode of system PLL IP parameter.

Connect this signal to the out_systempll_clk_<i> signal of the F-Tile Reference and System PLL Clocks Intel® FPGA IP.

clk_txmac Output 1 390.625 MHz Clock for TX section
clk_rxmac Output 1 390.625 MHz Clock for TX section
clk status Input 1 100 MHz Avalon® MM interface clock
reconfig_clk Input 1 100 MHz Transceiver reconfiguration clock