F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide

ID 758946
Date 1/09/2024
Public

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5.2.2. Bit Order For TX and RX Datapaths

The TX bit order matches the placement shown in the PCS lanes as illustrated in IEEE Standard for Ethernet, Section 4, Figure 49-5. The RX bit order matches the placement shown in IEEE Standard for Ethernet, Section 4, Figure 49-6.