F-Tile Low Latency 50G Ethernet Intel® FPGA Soft-IP User Guide

ID 758946
Date 5/10/2023

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Document Table of Contents

2. About this IP

The 50G Ethernet Intel FPGA IP implements the 25G & 50G Ethernet Specification, Draft 1.6 from the 25 Gigabit Ethernet Consortium and the IEEE 802.3by 25Gb Ethernet specification. The IP includes an option to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard. The MAC client side interface for the 50G Ethernet Intel FPGA IP is a 64-bit Avalon® streaming interface. It maps to two 25.78125 Gbps transceivers. Transceiver interface to 25GBASE-SR optical Physical Medium Dependent (PMD) transceiver is supported.

The F-Tile Low Latency 50G Ethernet Intel FPGA Soft-IP provides standard media access control (MAC) and physical coding sublayer (PCS), Reed-Solomon Forward Error Correction (RS-FEC), and PMA functions shown in the following block diagrams. The PHY comprises the PCS, optional RS-FEC, and elective PMA.

Figure 1.  F-Tile Low Latency 50G Ethernet MAC, PCS, and PMA IP Block Diagram

The following block diagram shows an example of a network application with 50G Ethernet Intel FPGA IP MAC and PHY.

Figure 2. Example Network Application