F-Tile Low Latency 50G Ethernet Intel® FPGA Soft-IP User Guide

ID 758946
Date 5/10/2023
Public

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Document Table of Contents

9. Document Revision History for the F-Tile Low Latency 50G Ethernet Intel FPGA Soft-IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.05.10 23.1 1.0.1
  • Renamed document title to F-Tile Low Latency 50G Ethernet Intel FPGA Soft-IP User Guide.
  • Updated references to "F-tile 50G Ethernet Intel FPGA IP" to "F-Tile Low Latency 50G Ethernet Intel FPGA Soft-IP".
  • Updated Specifying the IP Core Parameters and Options.
  • Updated F-Tile Low Latency 50G Ethernet Intel FPGA Soft-IP Parameters.
  • Made editorial edits throughout the document.
2023.05.05 23.1 1.0.1
  • Updated information in Release Information section.
  • Updated to O_tx_serial and i_tx_serial signals in Table: Transceiver Signals.
  • Updated Table: Transceiver Reconfiguration Interface Ports of the F-tile Ethernet Hard IP.
  • Updated the o_remote_fault_status signal in Table: Miscellaneous Status and Debug Signals.
  • Removed refclk_ref signal in Table: Clock Signals.
  • Updated Table: Hard IP Registers.
  • Updated product family name to Intel Agilex® 7.
2023.01.23 22.4 1.0.0 Initial release.