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1. About the F-Tile Low Latency 50G Ethernet Intel FPGA Soft-IP User Guide
2. About this IP
3. Getting Started
4. F-Tile Low Latency 50G Ethernet Intel FPGA Soft-IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. Document Revision History for the F-Tile Low Latency 50G Ethernet Intel FPGA Soft-IP User Guide
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5.1.5. 50 GbE RX PCS
The RX PCS datapath consists of:
- RX PCS descrambler—enables the incoming scrambled data to be descrambled.
- RX PCS decoder—decodes the incoming encoded data from the PMA interface.