F-Tile Low Latency 50G Ethernet Intel® FPGA Soft-IP User Guide

ID 758946
Date 5/10/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

1. About the F-Tile 50G Ethernet Intel® FPGA IP User Guide

Updated for:
Intel® Quartus® Prime Design Suite 23.1
IP Version 1.0.1
This user guide provides the features, architecture description, steps to instantiate, and guidelines about the 50G Ethernet Intel FPGA IP Intel® FPGA IP for the Intel Agilex® 7 (F-tile) devices.

Intended Audience

This document is intended for:

  • Design architect to make IP selection during system level design planning phase
  • Hardware designers when integrating the IP into their system level design
  • Validation engineers during system level simulation and hardware validation phase

Related Documents

The following table lists other reference documents which are related to the F-tile 50G Ethernet Intel FPGA IP protocol.
Table 1.  Related Documents
Reference Description
Low Latency 50G Ethernet Intel FPGA IP Intel® FPGA IP Release Notes Lists the changes made for the 50G Ethernet Intel FPGA IP Intel® FPGA IP in a particular release.

Acronyms and Glossary

Table 2.  Acronym List
Acronym Expansion
ALM Adaptive Logic Element
AVMM Avalon® memory-mapped interface
AVST Avalon® streaming interface
AXI ARM corporation's Advanced Extensible Interface
CRC Cyclic redundancy code
CSR Control and Status Register
EMIB Intel Embedded Silicon Bridge technology
FCQN Flow Control Queue Number
FPGA Field Programmable Gate Array
LAB Logic Array Block
MAC Media Access Control
MLAB Memory Logic Array Block
PCS Physical coding sublayer
PFC Priority-based flow control
PHY Physical layer
PLL Phase-locked loop
PMA Physical medium attachment
QN Queue Number