Nios® V Processor Software Developer Handbook

ID 743810
Date 10/06/2025
Public
Document Table of Contents

9.2.1.1. How the Hardware Works

The Nios® V processor can respond to traps including platform interrupts, timer interrupt, software interrupts and hardware exceptions. When the Nios® V processor responds to a trap, it performs the following tasks:

  • Disables interrupts by clearing mstatus.mie and saves the previous value to mstatus.mpie.
  • Saves the current program counter in Machine Exception Program Counter (mepc).
  • Saves the cause of the trap in Machine Cause register (mcause).
  • Switch to shadow register set if the ESI bit field in Shadow Register File Status register (msrfstatus.ESI) is enabled
  • Transfers control to the trap handling system (vector base address), held in the Machine Trap-Vector Base-Address (mtvec) register.
  • The same transfer of control is applied to all types of traps – interrupts and exceptions.

In CLINT-Direct mode, Nios® V processor traps are not vectored. Therefore, the same vector base address receives control for all types of traps. At the vector base address, the trap handler must determine the type of trap (i.e. hardware exception, platform interrupt, timer interrupt or software interrupt), and assign the relevant handler.

All Nios® V processor trap types are precise. This means that after a trap is handled, the Nios® V processor can re-execute the instruction that caused the trap.