1. Overview of Nios® V Embedded Processor Development
2. Getting Started with the Graphical User Interface
3. Getting Started from the Command Line
4. Nios® V Processor Software Development and Implementation
5. Nios® V Processor Board Support Package Editor
6. Overview of the Hardware Abstraction Layer
7. Developing Programs Using the Hardware Abstraction Layer
8. Developing Device Drivers for the Hardware Abstraction Layer
9. Trap Handling
10. Cache and Tightly-Coupled Memory
11. Error Correction Code (ECC) Handling
12. MicroC/OS-II Real-Time Operating System
13. MicroC/TCP-IP Protocol Stack
14. FreeRTOS* Real-Time Operating System
15. FreeRTOS-Plus-TCP Protocol Stack
16. Read-Only Zip File System
17. Publishing Component Information to Embedded Software
18. Nios® V Processor Appendix
19. Nios® V Processor Software Developer Handbook Archives
20. Revision History for the Nios® V Processor Software Developer Handbook
4.3.2.1. Selecting the Operating System
4.3.2.2. Intel HAL Configuration Tips
4.3.2.3. Micrium MicroC/OS-II Configuration tips
4.3.2.4. Configuring FreeRTOS*
4.3.2.5. Adding Software Package
4.3.2.6. Using Tcl Script with BSP Editor
4.3.2.7. Exporting Tcl Scripts with BSP Editor
4.3.2.8. Importing Tcl Script to Create a New BSP
7.1. HAL BSP Settings
7.2. The Nios® V Processor Embedded Project Structure
7.3. The system.h System Description File
7.4. Data Widths and the HAL Type Definitions
7.5. UNIX-Style Interface
7.6. File System
7.7. Using Character-Mode Devices
7.8. Using File System
7.9. Using Timer Devices
7.10. Using Flash Devices
7.11. Using DMA Devices
7.12. Reducing Code Footprint in Embedded Systems
7.13. Interrupt Controllers
7.14. Boot Sequence and Entry Point
7.15. Memory Usage
7.16. Working with HAL Source Files
7.12.1. Apply Compiler Flags
7.12.2. Use Small Variant Device Drivers
7.12.3. Reduce the File Descriptor Pool
7.12.4. Use /dev/null
7.12.5. Use a Smaller File I/O Library
7.12.6. Use the Minimal Character-Mode API
7.12.7. Eliminate Unused Device Drivers
7.12.8. Use the Picolibc Library
7.12.9. Eliminate Unused alt_load()
7.12.10. Eliminate Unneeded Exit Code
8.1. Driver Integration in the HAL API
8.2. The HAL Peripheral-Specific API
8.3. Preparing for HAL Driver Development
8.4. Development Flow for Creating Device Drivers
8.5. Nios® V Processor Hardware Design Concepts
8.6. Accessing Hardware
8.7. Creating Embedded Drivers for HAL Device Classes
8.8. Integrating a Device Driver in the HAL
8.9. Creating a Custom Device Driver for the HAL
8.10. Reducing Code Footprint in HAL Embedded Drivers
8.11. HAL Namespace Allocation
8.12. Overriding the HAL Default Device Drivers
8.8.5.2.1. Creating and Naming the Driver or Package
8.8.5.2.2. Identifying the Hardware Component Class
8.8.5.2.3. Setting the BSP Type
8.8.5.2.4. Specifying an Operating System
8.8.5.2.5. Specifying Source Files
8.8.5.2.6. Specifying a Subdirectory
8.8.5.2.7. Enabling Software Initialization
8.8.5.2.8. Adding Include Paths
8.8.5.2.9. Version Compatibility
9.5.1.1. Execute Time-Intensive Algorithms in the Application Context
9.5.1.2. Implement Time-Intensive Algorithms in Hardware
9.5.1.3. Increase Buffer Size
9.5.1.4. Use Double Buffering
9.5.1.5. Keep Interrupts Enabled
9.5.1.6. Use Fast Memory
9.5.1.7. Use a Separate Exception Stack
9.5.1.8. Use Nested Interrupts
9.5.1.9. Use Compiler Optimization
13.1. Overview of the MicroC/TCP-IP Protocol Stack
13.2. Support and Licensing
13.3. Prerequisites for Understanding the MicroC/TCP-IP Protocol Stack
13.4. Introduction to the MicroC/TCP-IP Protocol Stack - Nios® V Processor Edition
13.5. The MicroC/TCP-IP Protocol Stack Files and Directories
13.6. Enabling MicroC/TCP-IP Protocol Stack
13.7. Using the MicroC/TCP-IP Protocol Stack
15.1. Overview of the FreeRTOS-Plus-TCP
15.2. Support and Licensing
15.3. Prerequisites for Understanding the FreeRTOS-Plus-TCP Protocol Stack
15.4. Introduction to the FreeRTOS-Plus-TCP – Nios® V Processor Edition
15.5. FreeRTOS-Plus-TCP Files and Directories
15.6. Enabling FreeRTOS-Plus-TCP
15.7. Using the FreeRTOS-Plus-TCP Protocol Stack
18.1.1. HAL System Call
18.1.2. HAL Standard Types
18.1.3. HAL Platform Interrupt Management
18.1.4. HAL Software Interrupt Management
18.1.5. HAL Exception Management
18.1.6. HAL ECC Injection
18.1.7. HAL Cache Management
18.1.8. HAL DMA Device Management
18.1.9. HAL Flash Device Management
18.1.10. HAL Timer Device Management
18.1.11. HAL Code/Data Section Load
18.1.12. HAL File System Management
18.1.13. HAL Linked List Management
18.1.1.1. close()
18.1.1.2. execve()
18.1.1.3. _exit()
18.1.1.4. fcntl()
18.1.1.5. fork()
18.1.1.6. fstat()
18.1.1.7. getpid()
18.1.1.8. ioctl()
18.1.1.9. gettimeofday()
18.1.1.10. isatty()
18.1.1.11. kill()
18.1.1.12. link()
18.1.1.13. lseek()
18.1.1.14. open()
18.1.1.15. read()
18.1.1.16. _rename()
18.1.1.17. sbrk()
18.1.1.18. settimeofday()
18.1.1.19. stat()
18.1.1.20. unlink()
18.1.1.21. usleep()
18.1.1.22. wait()
18.1.1.23. write()
18.1.1.24. times()
18.1.3.1. alt_ic_irq_disable()
18.1.3.2. alt_ic_irq_enabled()
18.1.3.3. alt_ic_isr_register()
18.1.3.4. alt_ic_irq_enable()
18.1.3.5. alt_irq_cpu_enable_interrupts ()
18.1.3.6. alt_irq_disable_all()
18.1.3.7. alt_irq_enable_all()
18.1.3.8. alt_irq_enabled()
18.1.3.9. alt_irq_init()
18.1.3.10. alt_irq_pending ()
18.1.3.11. alt_clic_set_level ()
18.1.3.12. alt_clic_get_level ()
18.1.3.13. alt_clic_set_priority()
18.1.3.14. alt_clic_get_priority()
18.1.3.15. alt_clic_set_trigger_mode()
18.1.3.16. alt_clic_get_trigger_mode()
18.1.8.1. alt_dma_rxchan_depth()
18.1.8.2. alt_dma_rxchan_close()
18.1.8.3. alt_dma_rxchan_open()
18.1.8.4. alt_dma_rxchan_prepare()
18.1.8.5. alt_dma_rxchan_reg()
18.1.8.6. alt_dma_txchan_close()
18.1.8.7. alt_dma_txchan_ioctl()
18.1.8.8. alt_dma_txchan_open()
18.1.8.9. alt_dma_txchan_reg()
18.1.8.10. alt_dma_rxchan_ioctl()
18.1.8.11. alt_dma_txchan_space()
18.1.8.12. alt_dma_txchan_send()
18.5.2.1. add_memory_device
18.5.2.2. add_memory_region
18.5.2.3. add_section_mapping
18.5.2.4. are_same_resource
18.5.2.5. delete_memory_region
18.5.2.6. delete_section_mapping
18.5.2.7. disable_sw_package
18.5.2.8. enable_sw_package
18.5.2.9. get_addr_span
18.5.2.10. get_assignment
18.5.2.11. get_available_drivers
18.5.2.12. get_available_sw_packages
18.5.2.13. get_base_addr
18.5.2.14. get_break_offset
18.5.2.15. get_break_slave_desc
18.5.2.16. get_cpu_name
18.5.2.17. get_current_memory_regions
18.5.2.18. get_current_section_mappings
18.5.2.19. get_default_memory_regions
18.5.2.20. get_driver
18.5.2.21. get_enabled_sw_packages
18.5.2.22. get_exception_offset
18.5.2.23. get_exception_slave_desc
18.5.2.24. get_fast_tlb_miss_exception_offset
18.5.2.25. get_fast_tlb_miss_exception_slave_desc
18.5.2.26. get_interrupt_controller_id
18.5.2.27. get_irq_interrupt_controller_id
18.5.2.28. get_irq_number
18.5.2.29. get_memory_region
18.5.2.30. get_module_class_name
18.5.2.31. get_module_name
18.5.2.32. get_reset_offset
18.5.2.33. get_reset_slave_desc
18.5.2.34. get_section_mapping
18.5.2.35. get_setting
18.5.2.36. get_setting_desc
18.5.2.37. get_slave_descs
18.5.2.38. is_char_device
18.5.2.39. is_connected_interrupt_controller_device
18.5.2.40. is_connected_to_data_master
18.5.2.41. is_connected_to_instruction_master
18.5.2.42. is_ethernet_mac_device
18.5.2.43. is_flash
18.5.2.44. is_memory_device
18.5.2.45. is_non_volatile_storage
18.5.2.46. is_timer_device
18.5.2.47. log_debug
18.5.2.48. log_default
18.5.2.49. log_error
18.5.2.50. log_verbose
18.5.2.51. set_driver
18.5.2.52. set_ignore_file
18.5.2.53. set_setting
18.5.2.54. update_memory_region
18.5.2.55. update_section_mapping
18.5.2.56. add_default_memory_regions
18.5.2.57. create_bsp
18.5.2.58. generate_bsp
18.5.2.59. get_available_bsp_type_versions
18.5.2.60. get_available_bsp_types
18.5.2.61. get_available_cpu_architectures
18.5.2.62. get_available_cpu_names
18.5.2.63. get_available_software
18.5.2.64. get_available_software_setting_properties
18.5.2.65. get_available_software_settings
18.5.2.66. get_bsp_version
18.5.2.67. get_cpu_architecture
18.5.2.68. get_sopcinfo_file
18.5.2.69. get_supported_bsp_types
18.5.2.70. is_bsp_hal_extension
18.5.2.71. open_bsp
18.5.2.72. save_bsp
18.5.2.73. set_bsp_version
18.5.2.74. set_logging_mode
18.5.3.1. add_class_sw_setting
18.5.3.2. add_class_systemh_line
18.5.3.3. add_module_sw_property
18.5.3.4. add_module_sw_setting
18.5.3.5. add_module_systemh_line
18.5.3.6. add_systemh_line
18.5.3.7. get_class_peripheral
18.5.3.8. get_module_assignment
18.5.3.9. get_module_name
18.5.3.10. get_module_peripheral
18.5.3.11. get_module_sw_setting_value
18.5.3.12. get_peripheral_property
18.5.3.13. remove_class_systemh_line
18.5.3.14. remove_module_systemh_line
18.5.3.15. set_class_sw_setting_property
18.5.3.16. set_module_sw_setting_property
7.7.6.2. Extra Logging Options
In addition to the default boot messages, logging options are incorporated in Altera® FPGA logging. Each option is controlled by a C preprocessor symbol.
Name | Description | |
---|---|---|
System clock log | Purpose | Prints out a message from the system clock interrupt handler at a specified interval. This indicates that the system is still running. The default interval is every 1 second. |
Preprocessor symbol | ALT_LOG_SYS_CLK_ON_FLAG_SETTING | |
Modifiers | The system clock log has two modifiers, providing two different ways to specify the logging interval.
|
|
Sample Output | System Clock On 0 System Clock On 1 |
|
Write echo | Purpose | Every time alt_write() is called (normally, whenever characters are sent to stdout), the first <n> characters are echoed to a logging message. The message starts with the string "Write Echo:". <n> is specified with ALT_LOG_WRITE_ECHO_LEN. The default is 15 characters. |
Preprocessor symbol | ALT_LOG_WRITE_ON_FLAG_SETTING | |
Modifiers | ALT_LOG_WRITE_ECHO_LEN—Number of characters to echo. Default is 15. | |
Sample Output | Write Echo: Hello from Nios V | |
JTAG startup log | Purpose | At JTAG UART driver initialization, print out a line with the number of characters in the software transmit buffer followed by the JTAG UART control register contents. The number of characters, prefaced by the string "SW CirBuf", might be negative, because it is computed as (<tail_pointer> – <head_pointer>) on a circular buffer. For more information about the JTAG UART control register fields, refer to the Embedded Peripherals IP User Guide. |
Preprocessor symbol | ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING | |
Modifiers | None | |
Sample Output | JTAG Startup Info: SW CirBuf = 0, HW FIFO wspace=64 AC=0 WI=0 RI=0 WE=0 RE=1 | |
JTAG interval log | Purpose | Creates an alarm object to print out the same JTAG UART information as the JTAG startup log, but at a repeated interval. Default interval is 0.1 second, or 10 messages a second. |
Preprocessor symbol | ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING | |
Modifiers | The JTAG interval log has two modifiers, providing two different ways to specify the logging interval.
|
|
Sample Output | JTAG Alarm: SW CirBuf = 0, HW FIFO wspace=45 AC=0 WI=0 RI=0 WE=0 RE=1 | |
JTAG interrupt service routine (ISR) log | Purpose | Prints out a message every time the JTAG UART near-empty interrupt triggers. Message contains the same JTAG UART information as in the JTAG startup log. |
Preprocessor symbol | ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING | |
Modifiers | None | |
Sample Output | JTAG IRQ: SW CirBuf = -20, HW FIFO wspace=64 AC=0 WI=1 RI=0 WE=1 RE=1 | |
Boot log | Purpose | Prints out messages tracing the software boot process. The boot log is turned on by default when Altera® FPGA logging is enabled. |
Preprocessor symbol | ALT_LOG_BOOT_ON_FLAG_SETTING | |
Modifiers | None | |
Sample Output | For more information, refer to Enabling Logging. |
Note: An option’s modifiers are meaningful only when the option is enabled.
Setting a preprocessor flag to 1 enables the corresponding option. Any value other than 1 disables the option.
Several options have modifiers, which are additional preprocessor symbols controlling details of how the options work. For example, the system clock log’s modifiers control the logging interval.
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