Nios® V Processor Software Developer Handbook

ID 743810
Date 10/06/2025
Public
Document Table of Contents

9.2.3.2. How the Software Works

The trap handling system implementation is one of many possible implementations of a trap handling system for the Nios® V processor. Some features of the HAL trap handling system are constrained by the Nios® V hardware, while others provide generally useful services.

You can take advantage of the HAL trap handling system without a complete understanding of the HAL implementation.

For more information about how to install ISRs using the HAL API, refer to Interrupt Service Routines and Exception Handler.

Before implementing the CLIC, it is required to limit the alignment of mtvec to 64-byte boundaries for processor system. Alternatively, assign the .exception linker section to a memory region that fulfills the following conditions:
  • Start address is more than 0x40, and
  • Start address is a multiple of 0x10.
For example, 0x40, 0x50, 0x60 and etc are suitable starting addresses.
Figure 23. Exception Linker Section for CLIC