Nios® V Processor Software Developer Handbook

ID 743810
Date 10/06/2025
Public
Document Table of Contents

9.2.3.2.3. Interrupt Dispatcher

The interrupt dispatcher services all CLIC software-vectored interrupts. Note that the Nios V processor CLIC does not support hardware-vectored interrupts.

Pre-emption is allowed when the processor is executing an ISR under CLIC mode. However, you must fulfil these conditions for pre-emption to take effect:
  • You must configure the processor to support a minimum of 3 interrupt levels in the IP Parameter Editor. This is because the interrupt level 0 is dedicated to the application context. If there are only 2 interrupt levels, the processor is left with only 1 interrupt level for all interrupts.
  • You must assign unique levels to each interrupt during processor initialization. This is because pre-emption is not applicable between interrupts with the same level.
The interrupt dispatcher executes the following operation.
Table 46.  Interrupt Dispatcher Process Flow
Process Flow Notes on Pre-emption
1 Saves mepc and mcause register values onto the stack. Pre-emption is currently not allowed.
2 Gets the highest level, pending interrupt from mnxti register.
3 Enable interrupts
  1. Pre-emption is allowed.
  2. When the lower level, active interrupt is pre-empted, the processor control transfers to the trap handler.
  3. The re-entrant call to the trap handler creates a new stack frame, saves the register content and hart states, giving way to the higher-level interrupt.
  4. Once the higher-level ISR is completed, the processor returns to the lower-level interrupt.
4 Calls the appropriate ISR based on the return value from mnxti register.
5 After the ISR is completed, claim any pending interrupt with interrupt level higher than mcause.mpil.