Nios® V Processor Software Developer Handbook

ID 743810
Date 10/06/2025
Public
Document Table of Contents

9.2.3.2.1. Trap Handling System Structure

The trap handling system consists of the following components:

  • The trap handler
  • The interrupt dispatcher
    • ISR for timer interrupts
    • ISR for software interrupts
    • ISR for each peripheral that generates platform interrupts
  • The exception dispatcher
    • Handler for hardware exception
Nios® V processor CLIC supports software-vectored interrupts only. Thus, all traps start from the same trap handler. The trap handler manages the processor context switch and RTOS overhead (if any). Next, it determines the source of the trap before executing the correct dispatcher:
  • If the trap is an interrupt, the interrupt dispatcher is executed.
  • If the trap is an exception, the exception dispatcher is executed.

The interrupt dispatcher passes control to the relevant ISRs, while the exception dispatcher passes control to the correct exception handler. When the processor execution is within the interrupt dispatcher, pre-emption is allowed. When performing pre-emption, the processor temporarily pauses the currently executing interrupt handler to service a higher-priority interrupt.

The following files provides the HAL API for the trap handling system:

  • <Project directory>\software\bsp\HAL\src\intel_niosv_irq.c
  • <Project directory>\software\bsp\HAL\src\machine_trap.S
  • <Project directory>\software\bsp\HAL\src\alt_irq_handler.c
Figure 24. HAL Trap Handling System in CLIC-Mode
Table 45.  CLIC-Trap Handling
Traps Address Computation Action Taken
All Exceptions pc <= Exception Vector Enters trap handler
Machine software interrupt
Machine timer interrupt
Platform interrupt 0
Platform interrupt 16 (max. 2048)