Nios® V Processor Software Developer Handbook

ID 743810
Date 10/06/2025
Public
Document Table of Contents

11.3.1. How the Hardware Works

Like other exceptions, the Nios® V processor performs the following tasks when it responds to a ECC exception:
  • Disables interrupts by clearing mstatus.mie and saves the previous value to mstatus.mpie.
  • Disables ECC exception by clearing alt_ecc_status.global_ecc_exception_enable.
  • Saves the current program counter in Machine Exception Program Counter (mepc).
  • Saves Exception Code 19 – Hardware/ECC error in Machine Cause register (mcause).
  • Saves the identity of the afflicted memory in Machine Trap Value register (mtval)
  • Saves the ECC error memory source and error type in Machine Second Trap Value register (mtval2).
  • Transfers control to the vector base address, held in the Machine Trap-Vector Base-Address (mtvec) register.