Nios® V Processor Software Developer Handbook

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ID 743810
Date 10/06/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview of Nios® V Embedded Processor Development 2. Getting Started with the Graphical User Interface 3. Getting Started from the Command Line 4. Nios® V Processor Software Development and Implementation 5. Nios® V Processor Board Support Package Editor 6. Overview of the Hardware Abstraction Layer 7. Developing Programs Using the Hardware Abstraction Layer 8. Developing Device Drivers for the Hardware Abstraction Layer 9. Trap Handling 10. Cache and Tightly-Coupled Memory 11. Error Correction Code (ECC) Handling 12. MicroC/OS-II Real-Time Operating System 13. MicroC/TCP-IP Protocol Stack 14. FreeRTOS* Real-Time Operating System 15. FreeRTOS-Plus-TCP Protocol Stack 16. Read-Only Zip File System 17. Publishing Component Information to Embedded Software 18. Nios® V Processor Appendix 19. Nios® V Processor Software Developer Handbook Archives 20. Revision History for the Nios® V Processor Software Developer Handbook
1. Overview of Nios® V Embedded Processor Development x
1.1. Nios® V Processor Software Development Environment 1.2. Nios® V Processor Software Project Types 1.3. Nios® V Processor Development Tools 1.4. Nios® V Processor Software Programs
1.1. Nios® V Processor Software Development Environment x
1.1.1. Quartus® Prime Software Support
1.3. Nios® V Processor Development Tools x
1.3.1. Nios® V Processor Command Line Utilities Tools 1.3.2. Board Support Package Editor 1.3.3. Ashling* RiscFree* IDE for Altera FPGAs
1.4. Nios® V Processor Software Programs x
1.4.1. CMakeLists.txt and Nios® V Processor Tools
2. Getting Started with the Graphical User Interface x
2.1. Using Ashling* RiscFree* IDE for Altera® FPGAs 2.2. Using BSP Editor 2.3. Using Quartus Programmer
3. Getting Started from the Command Line x
3.1. Advantages of Command Line Software Development 3.2. Outline of the Nios® V Processor Tools Command Line
3.2. Outline of the Nios® V Processor Tools Command Line x
3.2.1. Command Line Utilities
3.2.1. Command Line Utilities x
3.2.1.1. niosv-bsp 3.2.1.2. niosv-app 3.2.1.3. niosv-download
4. Nios® V Processor Software Development and Implementation x
4.1. Nios® V Processor Tools 4.2. Nios® V Processor Software File Tree 4.3. Nios® V Processor Software Development Flow 4.4. Developing with the Hardware Abstraction Layer
4.1. Nios® V Processor Tools x
4.1.1. Nios® V Processor Tools Overview 4.1.2. Nios® V Processor Software Build Tools
4.1.2. Nios® V Processor Software Build Tools x
4.1.2.1. Nios® V Processor Software Build Tools Graphical User Interface 4.1.2.2. Nios® V Processor Software Build Tools Command Line Interface 4.1.2.3. What the Build Tools Create
4.1.2.1. Nios® V Processor Software Build Tools Graphical User Interface x
4.1.2.1.1. BSP Editor 4.1.2.1.2. Ashling* RiscFree* IDE for Altera FPGAs 4.1.2.1.3. Nios V Command Shell
4.1.2.2. Nios® V Processor Software Build Tools Command Line Interface x
4.1.2.2.1. Nios® V Processor Command Line Utilities 4.1.2.2.2. File Format Conversion Tools 4.1.2.2.3. Other Utilities Tools
4.1.2.3. What the Build Tools Create x
4.1.2.3.1. Applications and Libraries 4.1.2.3.2. Board Support Packages 4.1.2.3.3. CMakeLists.txt
4.2. Nios® V Processor Software File Tree x
4.2.1. Building Single Application and Single BSP 4.2.2. Building Single Application, Single Library, and BSP 4.2.3. Building Multiple Applications and Single BSP 4.2.4. Building BSP Library
4.2.1. Building Single Application and Single BSP x
4.2.1.1. Build Commands 4.2.1.2. File Tree Directory
4.2.2. Building Single Application, Single Library, and BSP x
4.2.2.1. Build Commands 4.2.2.2. File Tree Directory
4.2.3. Building Multiple Applications and Single BSP x
4.2.3.1. Build Commands 4.2.3.2. File Tree Directory
4.2.4. Building BSP Library x
4.2.4.1. Build Commands 4.2.4.2. File Tree Directory
4.3. Nios® V Processor Software Development Flow x
4.3.1. Getting Started 4.3.2. Configuring BSP Projects 4.3.3. Configuring the Application Project 4.3.4. Building and Running Nios® V Processor Software
4.3.2. Configuring BSP Projects x
4.3.2.1. Selecting the Operating System 4.3.2.2. Intel HAL Configuration Tips 4.3.2.3. Micrium MicroC/OS-II Configuration tips 4.3.2.4. Configuring FreeRTOS* 4.3.2.5. Adding Software Package 4.3.2.6. Using Tcl Script with BSP Editor 4.3.2.7. Exporting Tcl Scripts with BSP Editor 4.3.2.8. Importing Tcl Script to Create a New BSP
4.3.3. Configuring the Application Project x
4.3.3.1. Application Configuration Tips 4.3.3.2. Linking User Libraries
4.3.4. Building and Running Nios® V Processor Software x
4.3.4.1. Building the Nios® V Processor Software 4.3.4.2. Downloading and Running the Nios® V Processor Software 4.3.4.3. Nios® V Processor Software Debugging 4.3.4.4. Run Time Stack Checking 4.3.4.5. Ensuring Software Project Coherency
4.3.4.2. Downloading and Running the Nios® V Processor Software x
4.3.4.2.1. Communicating with the Target Device
4.3.4.5. Ensuring Software Project Coherency x
4.3.4.5.1. Recommended Development Practice 4.3.4.5.2. Recommended Architecture Practice
4.4. Developing with the Hardware Abstraction Layer x
4.4.1. Hardware Abstraction Layer Services 4.4.2. System Startup in HAL-based Application 4.4.3. HAL Peripheral Services 4.4.4. Handling Exceptions
4.4.1. Hardware Abstraction Layer Services x
4.4.1.1. HAL Configuration Options 4.4.1.2. Configuring the Boot Environment
4.4.2. System Startup in HAL-based Application x
4.4.2.1. System Initialization 4.4.2.2. crt0 Initialization 4.4.2.3. HAL Initialization
4.4.3. HAL Peripheral Services x
4.4.3.1. Timer Devices 4.4.3.2. Character Mode Devices 4.4.3.3. Flash Memory Devices
4.4.3.1. Timer Devices x
4.4.3.1.1. System Clock Timer 4.4.3.1.2. Timestamp Timer
4.4.3.2. Character Mode Devices x
4.4.3.2.1. stdin, stdout and stderr 4.4.3.2.2. Blocking versus Non-Blocking I/O 4.4.3.2.3. Adding Your Own Character Mode Device
4.4.3.3. Flash Memory Devices x
4.4.3.3.1. Memory Initialization, Querying, and Device Support 4.4.3.3.2. Accessing Flash Memory 4.4.3.3.3. Configuration and Use Limitations 4.4.3.3.4. Direct Memory Access Devices 4.4.3.3.5. Unsupported Devices
4.4.4. Handling Exceptions x
4.4.4.1. Modifying the Exception Handler
5. Nios® V Processor Board Support Package Editor x
5.1. Board Support Packages 5.2. Common BSP Tasks 5.3. Details of BSP Creation 5.4. Tcl Scripts for BSP Settings 5.5. Revising Your BSP 5.6. Specifying BSP Defaults 5.7. Device Drivers and Software Packages 5.8. Boot Configurations for Altera FPGA Embedded Software
5.1. Board Support Packages x
5.1.1. Overview of BSP Creation 5.1.2. Nios® V Processor BSP Components
5.1.2. Nios® V Processor BSP Components x
5.1.2.1. Hardware Abstraction Layer 5.1.2.2. newlib C Standard Library 5.1.2.3. Device Drivers 5.1.2.4. Optional Software Packages 5.1.2.5. Optional Real-Time Operating System
5.2. Common BSP Tasks x
5.2.1. Creating a BSP for an Altera FPGA Development Board 5.2.2. Adding the BSP Editor to Tool Flow 5.2.3. Linking and Locating 5.2.4. Other BSP Tasks
5.2.2. Adding the BSP Editor to Tool Flow x
5.2.2.1. Using Version Control 5.2.2.2. Copying, Moving, or Renaming a BSP 5.2.2.3. Passing the BSP to Another Developer
5.2.2.1. Using Version Control x
5.2.2.1.1. Creating BSP by Running User-defined Script to Call niosv-bsp 5.2.2.1.2. Creating Script that Uses the Command Line Tools
5.2.3. Linking and Locating x
5.2.3.1. Creating Memory Initialization Files 5.2.3.2. Modifying Linker Memory Regions 5.2.3.3. Creating a Custom Linker Section 5.2.3.4. Changing the Linker Section Mapping
5.2.3.3. Creating a Custom Linker Section x
5.2.3.3.1. Creating a Linker Section for an Existing Region 5.2.3.3.2. Dividing a Linker Region to Create a New Region and Section
5.2.4. Other BSP Tasks x
5.2.4.1. Querying Settings 5.2.4.2. Managing Device Drivers 5.2.4.3. Controlling the stdio Device 5.2.4.4. Configuring Optimization and Debugger Options 5.2.4.5. Configuring RISC-V Compiler
5.3. Details of BSP Creation x
5.3.1. BSP Settings File Creation 5.3.2. BSP Files and Folders 5.3.3. Linker Map Validation 5.3.4. Hierarchical Platform Designer Systems
5.3.2. BSP Files and Folders x
5.3.2.1. Generated and Copied Files 5.3.2.2. BSP Files
5.3.4. Hierarchical Platform Designer Systems x
5.3.4.1. Handling Hierarchical Systems
5.4. Tcl Scripts for BSP Settings x
5.4.1. Calling a Custom BSP Tcl Script
5.4.1. Calling a Custom BSP Tcl Script x
5.4.1.1. Tcl Script to Examine Hardware and Choose Settings
5.5. Revising Your BSP x
5.5.1. Regenerating Your BSP 5.5.2. Updating Your BSP 5.5.3. Recreating Your BSP
5.5.1. Regenerating Your BSP x
5.5.1.1. What Happens 5.5.1.2. When to Regenerate Your BSP
5.5.2. Updating Your BSP x
5.5.2.1. What Happens 5.5.2.2. When to Update Your BSP
5.5.3. Recreating Your BSP x
5.5.3.1. What Happens 5.5.3.2. When to Recreate Your BSP
5.6. Specifying BSP Defaults x
5.6.1. Top Level Tcl Script for BSP Defaults
5.6.1. Top Level Tcl Script for BSP Defaults x
5.6.1.1. Specifying the Default stdio Device 5.6.1.2. Specifying the Default System Timer 5.6.1.3. Specifying the Default Memory Map 5.6.1.4. Specifying the Default Bootloader Parameters 5.6.1.5. Specifying the Default Exception Parameter
5.8. Boot Configurations for Altera FPGA Embedded Software x
5.8.1. Memory Types 5.8.2. Boot from Flash Configuration 5.8.3. Run from Initialized Memory Configuration 5.8.4. Run-time Configurable Reset Configuration
6. Overview of the Hardware Abstraction Layer x
6.1. Getting Started with the Hardware Abstraction Layer 6.2. HAL Architecture for Embedded Software Systems 6.3. Embedded Hardware Supported by the HAL
6.2. HAL Architecture for Embedded Software Systems x
6.2.1. Services 6.2.2. Applications versus Drivers 6.2.3. Generic Device Models 6.2.4. C Standard Library—Newlib, Picolibc
6.2.3. Generic Device Models x
6.2.3.1. Device Model Classes 6.2.3.2. Benefits to Application Developers 6.2.3.3. Benefits to Device Driver Developers
6.3. Embedded Hardware Supported by the HAL x
6.3.1. Nios® V Processor Core Support 6.3.2. Supported Peripherals
6.3.2. Supported Peripherals x
6.3.2.1. Full HAL Support 6.3.2.2. Partial HAL Support
7. Developing Programs Using the Hardware Abstraction Layer x
7.1. HAL BSP Settings 7.2. The Nios® V Processor Embedded Project Structure 7.3. The system.h System Description File 7.4. Data Widths and the HAL Type Definitions 7.5. UNIX-Style Interface 7.6. File System 7.7. Using Character-Mode Devices 7.8. Using File System 7.9. Using Timer Devices 7.10. Using Flash Devices 7.11. Using DMA Devices 7.12. Reducing Code Footprint in Embedded Systems 7.13. Interrupt Controllers 7.14. Boot Sequence and Entry Point 7.15. Memory Usage 7.16. Working with HAL Source Files
7.7. Using Character-Mode Devices x
7.7.1. Standard Input, Standard Output and Standard Error 7.7.2. General Access to Character Mode Devices 7.7.3. C++ Streams 7.7.4. /dev/null 7.7.5. Lightweight Character-Mode I/O 7.7.6. Altera® FPGA Logging Functions
7.7.6. Altera® FPGA Logging Functions x
7.7.6.1. Enabling Logging 7.7.6.2. Extra Logging Options 7.7.6.3. Logging Levels 7.7.6.4. Example: Creating a BSP with Logging 7.7.6.5. Custom Logging Messages 7.7.6.6. Altera® FPGA Logging Files
7.9. Using Timer Devices x
7.9.1. System Clock Driver 7.9.2. Alarms 7.9.3. Timestamp Driver
7.10. Using Flash Devices x
7.10.1. Simple Flash Access 7.10.2. Block Erasure or Corruption 7.10.3. Fine-Grained Flash Access
7.10.3. Fine-Grained Flash Access x
7.10.3.1. alt_get_flash_info() 7.10.3.2. alt_erase_flash() 7.10.3.3. alt_write_flash_block()
7.11. Using DMA Devices x
7.11.1. DMA Transmit Channels 7.11.2. DMA Receive Channels
7.11.2. DMA Receive Channels x
7.11.2.1. Memory-to-Memory DMA Transactions
7.12. Reducing Code Footprint in Embedded Systems x
7.12.1. Apply Compiler Flags 7.12.2. Use Small Variant Device Drivers 7.12.3. Reduce the File Descriptor Pool 7.12.4. Use /dev/null 7.12.5. Use a Smaller File I/O Library 7.12.6. Use the Minimal Character-Mode API 7.12.7. Eliminate Unused Device Drivers 7.12.8. Use the Picolibc Library 7.12.9. Eliminate Unused alt_load() 7.12.10. Eliminate Unneeded Exit Code
7.12.1. Apply Compiler Flags x
7.12.1.1. Apply Different Compiler Flags in BSP and APP 7.12.1.2. Apply Different Compiler Flags within a Source File
7.12.5. Use a Smaller File I/O Library x
7.12.5.1. Definition of 'asnprintf()' 7.12.5.2. Use UNIX-Style File I/O 7.12.5.3. Emulate ANSI C Functions
7.12.10. Eliminate Unneeded Exit Code x
7.12.10.1. Eliminate Clean Exit 7.12.10.2. Eliminate All Exit Code 7.12.10.3. Turn off C++ Support
7.14. Boot Sequence and Entry Point x
7.14.1. Hosted Versus Free-Standing Applications 7.14.2. Boot Sequence for HAL-Based Programs 7.14.3. Customizing the Boot Sequence
7.14.2. Boot Sequence for HAL-Based Programs x
7.14.2.1. System Initialization Code Boot Sequence 7.14.2.2. Default Implementation Steps
7.15. Memory Usage x
7.15.1. Memory Sections 7.15.2. Assigning Code and Data to Memory Partitions 7.15.3. Placement of the Heap and Stack 7.15.4. Global Pointer Register 7.15.5. Boot Modes
7.15.2. Assigning Code and Data to Memory Partitions x
7.15.2.1. Simple Placement Options 7.15.2.2. Advanced Placement Options
7.16. Working with HAL Source Files x
7.16.1. Finding HAL Files 7.16.2. Overriding HAL Functions
8. Developing Device Drivers for the Hardware Abstraction Layer x
8.1. Driver Integration in the HAL API 8.2. The HAL Peripheral-Specific API 8.3. Preparing for HAL Driver Development 8.4. Development Flow for Creating Device Drivers 8.5. Nios® V Processor Hardware Design Concepts 8.6. Accessing Hardware 8.7. Creating Embedded Drivers for HAL Device Classes 8.8. Integrating a Device Driver in the HAL 8.9. Creating a Custom Device Driver for the HAL 8.10. Reducing Code Footprint in HAL Embedded Drivers 8.11. HAL Namespace Allocation 8.12. Overriding the HAL Default Device Drivers
8.5. Nios® V Processor Hardware Design Concepts x
8.5.1. The Relationship Between the .qsys File and system.h 8.5.2. Using the System Generation Tool to Optimize Hardware 8.5.3. Components, Devices, and Peripherals
8.7. Creating Embedded Drivers for HAL Device Classes x
8.7.1. Character-Mode Device Drivers 8.7.2. File Subsystem Drivers 8.7.3. Timer Device Drivers 8.7.4. Flash Device Drivers 8.7.5. DMA Device Drivers
8.7.1. Character-Mode Device Drivers x
8.7.1.1. Create a Device Instance 8.7.1.2. Register a Character Device
8.7.1.1. Create a Device Instance x
8.7.1.1.1. Modifying the Global Error Status, errno 8.7.1.1.2. Default Behavior for Functions Defined in alt_dev
8.7.2. File Subsystem Drivers x
8.7.2.1. Create a Device Instance 8.7.2.2. Register a File Subsystem Device
8.7.3. Timer Device Drivers x
8.7.3.1. System Clock Driver 8.7.3.2. Timestamp Driver
8.7.4. Flash Device Drivers x
8.7.4.1. Create a Flash Driver 8.7.4.2. Register a Flash Device
8.7.5. DMA Device Drivers x
8.7.5.1. DMA Transmit Channel 8.7.5.2. DMA Receive Channel
8.8. Integrating a Device Driver in the HAL x
8.8.1. Overview 8.8.2. Assumptions and Requirements 8.8.3. Nios® V Processor BSP Generation Flow 8.8.4. File Names and Locations 8.8.5. Driver and Software Package Tcl Script Creation
8.8.3. Nios® V Processor BSP Generation Flow x
8.8.3.1. Component Discovery 8.8.3.2. Device Driver Versions 8.8.3.3. Device Driver and Software Package Inclusion
8.8.3.3. Device Driver and Software Package Inclusion x
8.8.3.3.1. Specific Requests 8.8.3.3.2. No Specific Requests
8.8.4. File Names and Locations x
8.8.4.1. Source Code Discovery
8.8.5. Driver and Software Package Tcl Script Creation x
8.8.5.1. Example Device Driver File Hierarchy and Naming 8.8.5.2. Tcl Command Walkthrough for a Typical Driver or Software Package 8.8.5.3. Creating Settings for Device Drivers and Software Packages
8.8.5.2. Tcl Command Walkthrough for a Typical Driver or Software Package x
8.8.5.2.1. Creating and Naming the Driver or Package 8.8.5.2.2. Identifying the Hardware Component Class 8.8.5.2.3. Setting the BSP Type 8.8.5.2.4. Specifying an Operating System 8.8.5.2.5. Specifying Source Files 8.8.5.2.6. Specifying a Subdirectory 8.8.5.2.7. Enabling Software Initialization 8.8.5.2.8. Adding Include Paths 8.8.5.2.9. Version Compatibility
8.8.5.3. Creating Settings for Device Drivers and Software Packages x
8.8.5.3.1. How Settings Affect the Generated BSP 8.8.5.3.2. Data Types 8.8.5.3.3. Setting Destination Files 8.8.5.3.4. Setting Display Name 8.8.5.3.5. Setting Identifier 8.8.5.3.6. Setting Default Value 8.8.5.3.7. Setting Description 8.8.5.3.8. Setting Creation Example
8.9. Creating a Custom Device Driver for the HAL x
8.9.1. Header Files and alt_sys_init.c 8.9.2. Device Driver Source Code
8.9.1. Header Files and alt_sys_init.c x
8.9.1.1. Creating alt_sys_init.c Based on Associated Header Files
8.9.2. Device Driver Source Code x
8.9.2.1. altera_avalon_jtag_uart.h Defining Macros
9. Trap Handling x
9.1. Nios® V Processor Trap Handling Overview 9.2. Hardware Interrupt Controllers 9.3. Interrupt Service Routines 9.4. Latency and Response Time 9.5. Improving Nios® V Processor ISR Performance 9.6. Debugging Nios® V Processor ISRs
9.1. Nios® V Processor Trap Handling Overview x
9.1.1. Trap Handling Terminology
9.2. Hardware Interrupt Controllers x
9.2.1. CLINT-Direct Mode 9.2.2. CLINT-Vectored Mode 9.2.3. CLIC Mode
9.2.1. CLINT-Direct Mode x
9.2.1.1. How the Hardware Works 9.2.1.2. How the Software Works
9.2.1.2. How the Software Works x
9.2.1.2.1. Trap Handling System Structure 9.2.1.2.2. Trap Handler 9.2.1.2.3. Interrupt Dispatcher 9.2.1.2.4. Exception Dispatcher
9.2.1.2.2. Trap Handler x
9.2.1.2.2.1. Traps Occurs 9.2.1.2.2.2. Return from Traps
9.2.2. CLINT-Vectored Mode x
9.2.2.1. How the Hardware Works 9.2.2.2. How the Software Works
9.2.2.2. How the Software Works x
9.2.2.2.1. Trap Handling System Structure 9.2.2.2.2. Interrupt Service Routine 9.2.2.2.3. Exception Dispatcher
9.2.3. CLIC Mode x
9.2.3.1. How the Hardware Works 9.2.3.2. How the Software Works
9.2.3.2. How the Software Works x
9.2.3.2.1. Trap Handling System Structure 9.2.3.2.2. Trap Handler 9.2.3.2.3. Interrupt Dispatcher 9.2.3.2.4. Exception Dispatcher
9.2.3.2.2. Trap Handler x
9.2.3.2.2.1. Traps Occurs 9.2.3.2.2.2. Return from Traps
9.3. Interrupt Service Routines x
9.3.1. Platform Interrupt Service Routines (Basic) for CLINT & CLIC 9.3.2. Platform Interrupt Service Routines (Extended) for CLIC only 9.3.3. Software Interrupt Service Routines 9.3.4. Timer Interrupt Service Routine 9.3.5. Hardware Exception Handler
9.3.1. Platform Interrupt Service Routines (Basic) for CLINT & CLIC x
9.3.1.1. HAL APIs for Platform Interrupts 9.3.1.2. Writing a Platform ISR 9.3.1.3. Registering a Platform ISR 9.3.1.4. Enabling and Disabling Interrupts 9.3.1.5. C Example
9.3.1.1. HAL APIs for Platform Interrupts x
9.3.1.1.1. Enhanced HAL Hardware Interrupt API
9.3.1.2. Writing a Platform ISR x
9.3.1.2.1. Using Altera HAL Trap Handler in CLINT-Direct or CLIC Interrupt Mode 9.3.1.2.2. Running in a Restricted Environment
9.3.1.3. Registering a Platform ISR x
9.3.1.3.1. Methods the HAL Uses to Register the ISR
9.3.1.5. C Example x
9.3.1.5.1. Writing a Platform ISR to Service a Button PIO Interrupt 9.3.1.5.2. Registering the Button PIO ISR with the HAL
9.3.2. Platform Interrupt Service Routines (Extended) for CLIC only x
9.3.2.1. Enhanced HAL Hardware Interrupt and CLIC Interrupt Configuration API 9.3.2.2. Configuring CLIC Interrupt Level 9.3.2.3. Configuring CLIC Interrupt Priority 9.3.2.4. Configuring CLIC Interrupt Trigger Mode
9.3.3. Software Interrupt Service Routines x
9.3.3.1. HAL APIs for Software Interrupt 9.3.3.2. Writing a Software ISR 9.3.3.3. Registering a Software ISR 9.3.3.4. Enabling and Disabling Interrupts 9.3.3.5. C Example
9.3.3.5. C Example x
9.3.3.5.1. Writing a Software ISR 9.3.3.5.2. Registering the Software ISR with the HAL
9.3.5. Hardware Exception Handler x
9.3.5.1. Writing a Hardware Exception Handler 9.3.5.2. Registering a Hardware Exception Handler 9.3.5.3. Removing a Hardware Exception Handler 9.3.5.4. Debugging for Hardware Exception Handler
9.3.5.1. Writing a Hardware Exception Handler x
9.3.5.1.1. Exception Cause Codes
9.3.5.4. Debugging for Hardware Exception Handler x
9.3.5.4.1. Enable JTAG UART polling operation 9.3.5.4.2. Example of Hardware Exception Handler 9.3.5.4.3. Adding Custom Exception Handler
9.4. Latency and Response Time x
9.4.1. Direct or Vectored Mode 9.4.2. Shadow Register
9.5. Improving Nios® V Processor ISR Performance x
9.5.1. Software Performance Improvements 9.5.2. Hardware Performance Improvements
9.5.1. Software Performance Improvements x
9.5.1.1. Execute Time-Intensive Algorithms in the Application Context 9.5.1.2. Implement Time-Intensive Algorithms in Hardware 9.5.1.3. Increase Buffer Size 9.5.1.4. Use Double Buffering 9.5.1.5. Keep Interrupts Enabled 9.5.1.6. Use Fast Memory 9.5.1.7. Use a Separate Exception Stack 9.5.1.8. Use Nested Interrupts 9.5.1.9. Use Compiler Optimization
9.5.1.7. Use a Separate Exception Stack x
9.5.1.7.1. Separate Trap Stack
9.5.2. Hardware Performance Improvements x
9.5.2.1. Add Fast Memory 9.5.2.2. Add a DMA Controller 9.5.2.3. Place the Handler in Fast Memory 9.5.2.4. Select Platform Interrupt Priorities
9.5.2.4. Select Platform Interrupt Priorities x
9.5.2.4.1. Platform Interrupt Priorities with the CLINT
10. Cache and Tightly-Coupled Memory x
10.1. Nios® V Processor Cache Implementation 10.2. Initializing Cache after Reset 10.3. Device Driver Cache Considerations 10.4. Managing Cache in Multi-Master and Multi-Processor Systems 10.5. Tightly-Coupled Memory
11. Error Correction Code (ECC) Handling x
11.1. Nios® V Processor ECC Exception Overview 11.2. Single-bit & Double-bit ECC Error Injection 11.3. Single-bit & Double-bit ECC Error Exception Code 11.4. C Example
11.1. Nios® V Processor ECC Exception Overview x
11.1.1. Configuring ECC Capabilities
11.3. Single-bit & Double-bit ECC Error Exception Code x
11.3.1. How the Hardware Works 11.3.2. How the Software Works
11.3.2. How the Software Works x
11.3.2.1. ECC Handling System Structure 11.3.2.2. ECC Handling Code 11.3.2.3. Entering ECC Exception Handler
11.3.2.2. ECC Handling Code x
11.3.2.2.1. ECC Exception Occurs 11.3.2.2.2. Writeback Correctable Data
11.3.2.3. Entering ECC Exception Handler x
11.3.2.3.1. Writing ECC Exception Handler 11.3.2.3.2. Registering ECC Exception Handler 11.3.2.3.3. Removing ECC Exception Handler
12. MicroC/OS-II Real-Time Operating System x
12.1. Overview of the MicroC/OS-II RTOS 12.2. Other RTOS Providers 12.3. The Nios® V Processor Implementation of MicroC/OS-II 12.4. Implementing MicroC/OS-II Projects for the Nios® V Processor
12.1. Overview of the MicroC/OS-II RTOS x
12.1.1. Support and Licensing
12.3. The Nios® V Processor Implementation of MicroC/OS-II x
12.3.1. MicroC/OS-II Architecture 12.3.2. MicroC/OS-II Device Drivers 12.3.3. Thread-Safe Drivers 12.3.4. The newlib ANSI C Standard Library 12.3.5. Interrupt Service Routines for MicroC/OS-II
13. MicroC/TCP-IP Protocol Stack x
13.1. Overview of the MicroC/TCP-IP Protocol Stack 13.2. Support and Licensing 13.3. Prerequisites for Understanding the MicroC/TCP-IP Protocol Stack 13.4. Introduction to the MicroC/TCP-IP Protocol Stack - Nios® V Processor Edition 13.5. The MicroC/TCP-IP Protocol Stack Files and Directories 13.6. Enabling MicroC/TCP-IP Protocol Stack 13.7. Using the MicroC/TCP-IP Protocol Stack
13.4. Introduction to the MicroC/TCP-IP Protocol Stack - Nios® V Processor Edition x
13.4.1. Nios® V Processor System Requirements
13.7. Using the MicroC/TCP-IP Protocol Stack x
13.7.1. Initializing the Stack 13.7.2. Network IP configuration 13.7.3. Example applications
13.7.3. Example applications x
13.7.3.1. simple_socket_server.c 13.7.3.2. app_iperf.c
14. FreeRTOS* Real-Time Operating System x
14.1. Overview of the FreeRTOS* 14.2. The Nios® V Processor Implementation of FreeRTOS* 14.3. Implementing FreeRTOS™ Project for the Nios® V Processor
14.1. Overview of the FreeRTOS* x
14.1.1. Support and Licensing
14.2. The Nios® V Processor Implementation of FreeRTOS* x
14.2.1. FreeRTOS* Architecture 14.2.2. FreeRTOS* Device Drivers 14.2.3. Thread-Safe HAL Drivers 14.2.4. The newlib ANSI C Standard Library
14.3. Implementing FreeRTOS™ Project for the Nios® V Processor x
14.3.1. Create FreeRTOS BSP Project 14.3.2. Configure FreeRTOS Features 14.3.3. Write FreeRTOS-based Source Codes 14.3.4. Generate Application CMake File 14.3.5. Build FreeRTOS BSP and Application Projects 14.3.6. Integrating Device Drivers
14.3.6. Integrating Device Drivers x
14.3.6.1. Integrating Device Drivers without Initialization Manually 14.3.6.2. Integrating Device Drivers with Initialization Manually
15. FreeRTOS-Plus-TCP Protocol Stack x
15.1. Overview of the FreeRTOS-Plus-TCP 15.2. Support and Licensing 15.3. Prerequisites for Understanding the FreeRTOS-Plus-TCP Protocol Stack 15.4. Introduction to the FreeRTOS-Plus-TCP – Nios® V Processor Edition 15.5. FreeRTOS-Plus-TCP Files and Directories 15.6. Enabling FreeRTOS-Plus-TCP 15.7. Using the FreeRTOS-Plus-TCP Protocol Stack
15.4. Introduction to the FreeRTOS-Plus-TCP – Nios® V Processor Edition x
15.4.1. Nios® V Processor System Requirements
16. Read-Only Zip File System x
16.1. Read-Only Zip File System in BSP Editor 16.2. Preparing the Zip File 16.3. Programming the Zip File to Flash 16.4. Programming the Zip File to On-Chip ROM
16.3. Programming the Zip File to Flash x
16.3.1. General Purpose QSPI Flash 16.3.2. Active Serial Configuration Flash in Control-block Based Devices 16.3.3. Active Serial Configuration Flash in SDM Based Devices
17. Publishing Component Information to Embedded Software x
17.1. Embedded Component Information Flow 17.2. Embedded Software Assignments
17.2. Embedded Software Assignments x
17.2.1. C Macro Namespace 17.2.2. Configuration Namespace
17.2.1. C Macro Namespace x
17.2.1.1. Generated Macro in system.h 17.2.1.2. GCC C/C++ 32-bit Processor Constants
17.2.2. Configuration Namespace x
17.2.2.1. Configuration Data Types 17.2.2.2. Component Configuration Information 17.2.2.3. Memory-Mapped Slave Information
18. Nios® V Processor Appendix x
18.1. HAL API 18.2. Nios® V Processor Tools Reference 18.3. GNU RISC-V Embedded GCC Toolchain Reference 18.4. Settings Managed by Nios® V Processor Board Support Package Editor 18.5. Board Support Package Tcl Commands 18.6. Nios® V Processor Design Example 18.7. Manual System PATH Variable Setup
18.1. HAL API x
18.1.1. HAL System Call 18.1.2. HAL Standard Types 18.1.3. HAL Platform Interrupt Management 18.1.4. HAL Software Interrupt Management 18.1.5. HAL Exception Management 18.1.6. HAL ECC Injection 18.1.7. HAL Cache Management 18.1.8. HAL DMA Device Management 18.1.9. HAL Flash Device Management 18.1.10. HAL Timer Device Management 18.1.11. HAL Code/Data Section Load 18.1.12. HAL File System Management 18.1.13. HAL Linked List Management
18.1.1. HAL System Call x
18.1.1.1. close() 18.1.1.2. execve() 18.1.1.3. _exit() 18.1.1.4. fcntl() 18.1.1.5. fork() 18.1.1.6. fstat() 18.1.1.7. getpid() 18.1.1.8. ioctl() 18.1.1.9. gettimeofday() 18.1.1.10. isatty() 18.1.1.11. kill() 18.1.1.12. link() 18.1.1.13. lseek() 18.1.1.14. open() 18.1.1.15. read() 18.1.1.16. _rename() 18.1.1.17. sbrk() 18.1.1.18. settimeofday() 18.1.1.19. stat() 18.1.1.20. unlink() 18.1.1.21. usleep() 18.1.1.22. wait() 18.1.1.23. write() 18.1.1.24. times()
18.1.2. HAL Standard Types x
18.1.2.1. alt_getchar() 18.1.2.2. alt_putstr() 18.1.2.3. alt_putchar() 18.1.2.4. alt_printf()
18.1.3. HAL Platform Interrupt Management x
18.1.3.1. alt_ic_irq_disable() 18.1.3.2. alt_ic_irq_enabled() 18.1.3.3. alt_ic_isr_register() 18.1.3.4. alt_ic_irq_enable() 18.1.3.5. alt_irq_cpu_enable_interrupts () 18.1.3.6. alt_irq_disable_all() 18.1.3.7. alt_irq_enable_all() 18.1.3.8. alt_irq_enabled() 18.1.3.9. alt_irq_init() 18.1.3.10. alt_irq_pending () 18.1.3.11. alt_clic_set_level () 18.1.3.12. alt_clic_get_level () 18.1.3.13. alt_clic_set_priority() 18.1.3.14. alt_clic_get_priority() 18.1.3.15. alt_clic_set_trigger_mode() 18.1.3.16. alt_clic_get_trigger_mode()
18.1.4. HAL Software Interrupt Management x
18.1.4.1. alt_niosv_enable_msw_interrupt() 18.1.4.2. alt_niosv_disable_msw_interrupt() 18.1.4.3. alt_niosv_is_msw_interrupt_enabled() 18.1.4.4. alt_niosv_trigger_msw_interrupt() 18.1.4.5. alt_niosv_clear_msw_interrupt() 18.1.4.6. alt_niosv_register_msw_interrupt_handler()
18.1.5. HAL Exception Management x
18.1.5.1. alt_instruction_exception_register() 18.1.5.2. alt_ecc_exception_register()
18.1.6. HAL ECC Injection x
18.1.6.1. alt_ecc_error_inject()
18.1.7. HAL Cache Management x
18.1.7.1. alt_dcache_flush() 18.1.7.2. alt_dcache_flush_all() 18.1.7.3. alt_dcache_flush_no_writeback() 18.1.7.4. alt_icache_flush_all() 18.1.7.5. alt_icache_flush()
18.1.8. HAL DMA Device Management x
18.1.8.1. alt_dma_rxchan_depth() 18.1.8.2. alt_dma_rxchan_close() 18.1.8.3. alt_dma_rxchan_open() 18.1.8.4. alt_dma_rxchan_prepare() 18.1.8.5. alt_dma_rxchan_reg() 18.1.8.6. alt_dma_txchan_close() 18.1.8.7. alt_dma_txchan_ioctl() 18.1.8.8. alt_dma_txchan_open() 18.1.8.9. alt_dma_txchan_reg() 18.1.8.10. alt_dma_rxchan_ioctl() 18.1.8.11. alt_dma_txchan_space() 18.1.8.12. alt_dma_txchan_send()
18.1.9. HAL Flash Device Management x
18.1.9.1. alt_flash_close_dev() 18.1.9.2. alt_erase_flash_block() 18.1.9.3. alt_flash_open_dev() 18.1.9.4. alt_get_flash_info() 18.1.9.5. alt_read_flash() 18.1.9.6. alt_write_flash() 18.1.9.7. alt_write_flash_block() 18.1.9.8. alt_lock_flash()
18.1.10. HAL Timer Device Management x
18.1.10.1. alt_alarm_start() 18.1.10.2. alt_alarm_stop() 18.1.10.3. alt_nticks() 18.1.10.4. alt_tick() 18.1.10.5. alt_ticks_per_second() 18.1.10.6. alt_sysclk_init() 18.1.10.7. alt_timestamp() 18.1.10.8. alt_timestamp_freq() 18.1.10.9. alt_timestamp_start()
18.1.11. HAL Code/Data Section Load x
18.1.11.1. alt_load_section()
18.1.12. HAL File System Management x
18.1.12.1. alt_fs_reg()
18.1.13. HAL Linked List Management x
18.1.13.1. alt_llist_insert() 18.1.13.2. alt_llist_remove()
18.2. Nios® V Processor Tools Reference x
18.2.1. Nios® V Processor Command Line Utilities 18.2.2. File Format Conversion Tools Reference 18.2.3. Other Command Line Utilities Tools Reference
18.2.1. Nios® V Processor Command Line Utilities x
18.2.1.1. niosv-shell 18.2.1.2. niosv-bsp 18.2.1.3. niosv-app 18.2.1.4. niosv-download 18.2.1.5. niosv-stack-report
18.2.2. File Format Conversion Tools Reference x
18.2.2.1. elf2hex 18.2.2.2. elf2flash
18.2.3. Other Command Line Utilities Tools Reference x
18.2.3.1. juart-terminal 18.2.3.2. cmake 18.2.3.3. make 18.2.3.4. OpenOCD 18.2.3.5. openocd-cfg-gen 18.2.3.6. elf-insert 18.2.3.7. elf-query
18.4. Settings Managed by Nios® V Processor Board Support Package Editor x
18.4.1. Overview of BSP Settings 18.4.2. Overview of Component and Driver Settings 18.4.3. BSP Settings Reference
18.4.2. Overview of Component and Driver Settings x
18.4.2.1. Altera FPGA Avalon-MM JTAG UART Driver Settings 18.4.2.2. Altera FPGA Avalon-MM UART Driver Settings
18.4.3. BSP Settings Reference x
18.4.3.1. Intel HAL BSP 18.4.3.2. Micrium MicroC/OS-II BSP 18.4.3.3. FreeRTOS BSP 18.4.3.4. Device Drivers BSP
18.5. Board Support Package Tcl Commands x
18.5.1. Tcl Command Environments 18.5.2. Tcl Commands for BSP Settings 18.5.3. Tcl Commands for BSP Generation Callbacks 18.5.4. Tcl Commands for Drivers and Packages
18.5.2. Tcl Commands for BSP Settings x
18.5.2.1. add_memory_device 18.5.2.2. add_memory_region 18.5.2.3. add_section_mapping 18.5.2.4. are_same_resource 18.5.2.5. delete_memory_region 18.5.2.6. delete_section_mapping 18.5.2.7. disable_sw_package 18.5.2.8. enable_sw_package 18.5.2.9. get_addr_span 18.5.2.10. get_assignment 18.5.2.11. get_available_drivers 18.5.2.12. get_available_sw_packages 18.5.2.13. get_base_addr 18.5.2.14. get_break_offset 18.5.2.15. get_break_slave_desc 18.5.2.16. get_cpu_name 18.5.2.17. get_current_memory_regions 18.5.2.18. get_current_section_mappings 18.5.2.19. get_default_memory_regions 18.5.2.20. get_driver 18.5.2.21. get_enabled_sw_packages 18.5.2.22. get_exception_offset 18.5.2.23. get_exception_slave_desc 18.5.2.24. get_fast_tlb_miss_exception_offset 18.5.2.25. get_fast_tlb_miss_exception_slave_desc 18.5.2.26. get_interrupt_controller_id 18.5.2.27. get_irq_interrupt_controller_id 18.5.2.28. get_irq_number 18.5.2.29. get_memory_region 18.5.2.30. get_module_class_name 18.5.2.31. get_module_name 18.5.2.32. get_reset_offset 18.5.2.33. get_reset_slave_desc 18.5.2.34. get_section_mapping 18.5.2.35. get_setting 18.5.2.36. get_setting_desc 18.5.2.37. get_slave_descs 18.5.2.38. is_char_device 18.5.2.39. is_connected_interrupt_controller_device 18.5.2.40. is_connected_to_data_master 18.5.2.41. is_connected_to_instruction_master 18.5.2.42. is_ethernet_mac_device 18.5.2.43. is_flash 18.5.2.44. is_memory_device 18.5.2.45. is_non_volatile_storage 18.5.2.46. is_timer_device 18.5.2.47. log_debug 18.5.2.48. log_default 18.5.2.49. log_error 18.5.2.50. log_verbose 18.5.2.51. set_driver 18.5.2.52. set_ignore_file 18.5.2.53. set_setting 18.5.2.54. update_memory_region 18.5.2.55. update_section_mapping 18.5.2.56. add_default_memory_regions 18.5.2.57. create_bsp 18.5.2.58. generate_bsp 18.5.2.59. get_available_bsp_type_versions 18.5.2.60. get_available_bsp_types 18.5.2.61. get_available_cpu_architectures 18.5.2.62. get_available_cpu_names 18.5.2.63. get_available_software 18.5.2.64. get_available_software_setting_properties 18.5.2.65. get_available_software_settings 18.5.2.66. get_bsp_version 18.5.2.67. get_cpu_architecture 18.5.2.68. get_sopcinfo_file 18.5.2.69. get_supported_bsp_types 18.5.2.70. is_bsp_hal_extension 18.5.2.71. open_bsp 18.5.2.72. save_bsp 18.5.2.73. set_bsp_version 18.5.2.74. set_logging_mode
18.5.3. Tcl Commands for BSP Generation Callbacks x
18.5.3.1. add_class_sw_setting 18.5.3.2. add_class_systemh_line 18.5.3.3. add_module_sw_property 18.5.3.4. add_module_sw_setting 18.5.3.5. add_module_systemh_line 18.5.3.6. add_systemh_line 18.5.3.7. get_class_peripheral 18.5.3.8. get_module_assignment 18.5.3.9. get_module_name 18.5.3.10. get_module_peripheral 18.5.3.11. get_module_sw_setting_value 18.5.3.12. get_peripheral_property 18.5.3.13. remove_class_systemh_line 18.5.3.14. remove_module_systemh_line 18.5.3.15. set_class_sw_setting_property 18.5.3.16. set_module_sw_setting_property
18.5.4. Tcl Commands for Drivers and Packages x
18.5.4.1. add_sw_property 18.5.4.2. add_sw_setting 18.5.4.3. add_sw_setting2 18.5.4.4. create_driver 18.5.4.5. create_os 18.5.4.6. create_sw_package 18.5.4.7. set_sw_property 18.5.4.8. set_sw_setting_property
18.6. Nios® V Processor Design Example x
18.6.1. FPGA Design Store 18.6.2. Quartus® Prime Software 18.6.3. Migrating to Other FPGA Device
18.6.2. Quartus® Prime Software x
18.6.2.1. Configurable Example Design
1. Overview of Nios® V Embedded Processor Development
2. Getting Started with the Graphical User Interface
3. Getting Started from the Command Line
4. Nios® V Processor Software Development and Implementation
5. Nios® V Processor Board Support Package Editor
6. Overview of the Hardware Abstraction Layer
7. Developing Programs Using the Hardware Abstraction Layer
8. Developing Device Drivers for the Hardware Abstraction Layer
9. Trap Handling
10. Cache and Tightly-Coupled Memory
11. Error Correction Code (ECC) Handling
12. MicroC/OS-II Real-Time Operating System
13. MicroC/TCP-IP Protocol Stack
14. FreeRTOS* Real-Time Operating System
15. FreeRTOS-Plus-TCP Protocol Stack
16. Read-Only Zip File System
17. Publishing Component Information to Embedded Software
18. Nios® V Processor Appendix
19. Nios® V Processor Software Developer Handbook Archives
20. Revision History for the Nios® V Processor Software Developer Handbook

9.2.2.1. How the Hardware Works

The Nios® V processor can respond to traps including platform interrupts, timer interrupt, hardware interrupts and hardware exceptions. When the Nios® V processor responds to a trap, it performs the following tasks:

  • Disables interrupts by clearing mstatus.mie and saves the previous value to mstatus.mpie.
  • Saves the current program counter address in Machine Exception Program Counter (mepc).
  • Saves the cause of the trap in the Machine Cause register (mcause).
  • Switch to shadow register set if the ESI bit field in Shadow Register File Status register (msrfstatus.ESI) is enabled
  • For exception – Transfers control to the exception dispatcher. The vector table base address (held in the mtvec register) contains the jump instruction to the exception dispatcher.
  • For interrupt – Transfer control to the interrupt ISR. Each interrupt vector contains the jump instruction to the individual ISRs. The processor calculates the interrupt vector, by adding vector table base address to four times the interrupt cause number.

In CLINT-Vectored mode Nios® V traps are vectored. It is implemented using a vector table, that holds jump instruction to the associated ISR. The code in the Machine Cause register (mcause) determines which jump instruction is executed.

All Nios® V processor trap types are precise. This means that after a trap is handled, the Nios® Vprocessor can re-execute the instruction that caused the trap.

For more information about Machine Trap Handling CSRs behaviour, refer to the Processor Reference Manual.

Related Information
Level Two Title