The Triple-Speed Ethernet Intel® FPGA IP for Intel® Agilex™ provides the capability of generating design examples for selected configurations, which allows you to:
- Compile the design to get an estimate of the IP area usage and timing.
- Simulate the design to verify the IP functionality through simulation.
- Test the design on the hardware using the Intel® Agilex™ I-Series Transceiver-SoC Development Kit.
When you generate a design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
Note: Hardware support is currently not available in the Intel® Quartus® Prime Pro Edition Software version 22.3.
Note: In Intel® Quartus® Prime Pro Edition Software version 22.3, a patch is required to avoid simulation failure on the design example. For more information, refer to the KDB link: Why does simulation fail for the Triple-Speed Ethernet Intel FPGA IP Multiport Design Example?.