Triple-Speed Ethernet Intel Agilex FPGA IP Design Example User Guide

ID 741330
Date 12/09/2022

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2.1. Features

  • Generates the design example for Triple-Speed Ethernet Multiport Ethernet MAC without Internal FIFO and PCS with LVDS I/O using multi-channel shared FIFO.
  • Generates traffic at the transmit path and validates received data through the transceiver LVDS I/O external loopback.
  • Tx and RX serial external loopback mode through LVDS I/O.
  • Supports only external loopback.
  • Supports only four ports.