MACsec Intel® FPGA IP User Guide

ID 736108
Date 6/26/2023

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Document Table of Contents

7.2. Steps to Run Simulation

Follow the steps below to run the design example in simulation:
  1. Create a project using one of the above devices.
  2. Create a MACsec IP variant using the above parameters for the device you have selected.
  3. Click the Generate Example Design button. The Select Example Design Directory appears.
  4. Select the directory where you want the Example Design to be placed.
  5. Click OK. Your design example is now generated in your chosen directory.
  6. Navigate to the <Example Design Directory>/example_testbench/.
  7. Execute a proper command to kick off simulation in your supported simulator.
Note: The MACsec Design Example incorporates the Crypto ICA Hard IP. You can integrate your own soft Crypto IP by setting CRYPTO_QHIP_EN to '0', which exposes the Crypto interfaces as shown in Crypto RX Interface and Crypto TX Interface. This configuration has not yet been validated or verified.
The table below shows the steps to simulate the testbench.
Table 61.  Steps to Simulate the Testbench
Simulator Instructions
Synopsys* VCS*

In the command line, type:


Synopsys VCS MX

In the command line, type:


Use this script when the design contains Verilog HDL and System Verilog with VHDL.

QuestaSim* or Questa* Intel FPGA Edition

In the command line, type:

vsim -do

If you prefer to simulate without bringing up the GUI, type:

vsim -c -do

The figure below shows a sample output of the simulation.
Figure 32. Simulation Output