MACsec Intel® FPGA IP User Guide

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ID 736108
Date 6/26/2023
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Functional Description 6. Configuration Registers for MACsec IP 7. MACsec Intel® FPGA IP Example Design 8. MACsec Intel FPGA IP User Guide Archives 9. Document Revision History for the MACsec Intel FPGA IP User Guide
1. Introduction x
1.1. Terminology 1.2. IP Core Overview 1.3. Release Information 1.4. Device Family Support 1.5. Device Speed Grade Support and Theoretical Throughput 1.6. Resource Utilization
1.2. IP Core Overview x
1.2.1. IP Description 1.2.2. IP Core Applications
1.2.2. IP Core Applications x
1.2.2.1. SmartNIC 1.2.2.2. Ethernet Bridge + Inline MACsec
2. Interface Overview x
2.1. Block Diagram 2.2. Interfaces 2.3. Clocking Domains
2.2. Interfaces x
2.2.1. IP Interface Signals 2.2.2. IP Interface Signal Timing Diagram/Waveforms 2.2.3. Clocks, Resets, and Interrupts
2.2.1. IP Interface Signals x
2.2.1.1. Common Port Mux Interface 2.2.1.2. Common Port Demux Interface 2.2.1.3. Controlled Port Mux Interface 2.2.1.4. Controlled Port Demux Interface 2.2.1.5. Uncontrolled Port RX Interface 2.2.1.6. Uncontrolled Port TX Interface 2.2.1.7. Crypto RX Interface 2.2.1.8. Crypto TX Interface 2.2.1.9. Management Interface 2.2.1.10. Decrypt Port Mux Management Interface 2.2.1.11. Decrypt Port Demux Management Interface 2.2.1.12. Encrypt Port Mux Management Interface 2.2.1.13. Encrypt Port Demux Management Interface 2.2.1.14. Crypto IP Management Bus 2.2.1.15. Miscellaneous Control Signals
2.2.2. IP Interface Signal Timing Diagram/Waveforms x
2.2.2.1. Common Port Mux Interface Waveform 2.2.2.2. Common Port Demux Interface Waveform 2.2.2.3. Controlled Port Mux Interface Waveform 2.2.2.4. Controlled Port Demux Interface Waveform 2.2.2.5. Uncontrolled Port RX Interface Waveform 2.2.2.6. Uncontrolled Port TX Interface Waveform 2.2.2.7. Crypto RX Waveform 2.2.2.8. Crypto TX Waveform 2.2.2.9. MACsec Management Interface (Read) 2.2.2.10. MACsec Management Interface (Write)
3. Parameters x
3.1. MACsec Intel FPGA IP Parameter Settings
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Reset Transactions 4.5. MACsec Software Initialization Sequence
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
5. Functional Description x
5.1. AXI-ST Common/Controlled/Uncontrolled Ports 5.2. Packet Parser and Classifier 5.3. SA Lookup and Update 5.4. Encryption Framer/DeFramer 5.5. Decryption Framer/Deframer 5.6. Packet Aggregator/Disaggregator 5.7. Cryptographic AES 5.8. Error Handling 5.9. Packet Statistics
5.1. AXI-ST Common/Controlled/Uncontrolled Ports x
5.1.1. AXI-ST Single Packet Mode 5.1.2. AXI-ST Multi Packet Mode 5.1.3. User Interface Data Streaming 5.1.4. AXI-ST Ready Latency 5.1.5. Port and Secure Channel Mapping 5.1.6. Port and Crypto Channel Mapping 5.1.7. Minimum Packet Size 5.1.8. Byte Ordering 5.1.9. Controlled/Uncontrolled Port Muxing
5.1.3. User Interface Data Streaming x
5.1.3.1. Single Packet Mode Data Stream 5.1.3.2. Multi Packet Mode Data Stream
5.2. Packet Parser and Classifier x
5.2.1. Packet Parser 5.2.2. Packet Classifier
5.3. SA Lookup and Update x
5.3.1. Packet Actions 5.3.2. Packet Buffer 5.3.3. New Channel Assignment 5.3.4. Anti-Replay Protection
5.3.1. Packet Actions x
5.3.1.1. Packet Encrypt 5.3.1.2. Packet Decrypt 5.3.1.3. Packet Discard 5.3.1.4. PDU Validation
5.4. Encryption Framer/DeFramer x
5.4.1. Channel Allocation 5.4.2. Packet Framer 5.4.3. VLAN Tagging
5.4.2. Packet Framer x
5.4.2.1. Bypass Packet 5.4.2.2. Stream Interleaving
5.4.3. VLAN Tagging x
5.4.3.1. No VLAN Tag 5.4.3.2. VLAN Tag (Not in Clear) 5.4.3.3. VLAN Tag (Clear)
5.5. Decryption Framer/Deframer x
5.5.1. XPN Recovery 5.5.2. Replay Check Update 5.5.3. Packet Deframer
5.6. Packet Aggregator/Disaggregator x
5.6.1. Packet Aggregator 5.6.2. Packet Disaggregator
5.7. Cryptographic AES x
5.7.1. Register Address Ordering 5.7.2. Byte Order Swapping 5.7.3. Byte Ordering
5.8. Error Handling x
5.8.1. Packet Error Handling 5.8.2. Memory Blocks ECC Errors 5.8.3. Crypto Errors 5.8.4. System-Level Errors
7. MACsec Intel® FPGA IP Example Design x
7.1. Simulation Requirements 7.2. Steps to Run Simulation 7.3. Port Configurations 7.4. Multi Interface Buffering Muxing/Demuxing 7.5. 2x25 GbE (Encryption + Decryption) 7.6. Packet Generator/Checker 7.7. Clocking
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Functional Description
6. Configuration Registers for MACsec IP
7. MACsec Intel® FPGA IP Example Design
8. MACsec Intel FPGA IP User Guide Archives
9. Document Revision History for the MACsec Intel FPGA IP User Guide

2.2.1.8. Crypto TX Interface

This interface is only exposed when CRYPTO_QHIP_EN = 0. This setting is not recommended.

Note: For more information on how to use this interface, refer to Symmetric Cryptographic Intel FPGA Hard IP User Guide.
Table 14.  Crypto TX Interface
Signal Name Width Direction Description
app_ip_st_clk 1 Input Clock
app_ip_st_areset_n 1 Input Asynchronous reset
aes_ip_app_tx_tvalid 1 Output Valid
aes_ip_app_tx_tdata 512 Output Data
aes_app_ip_tx_tready 1 Input Ready
aes_ip_app_tx_tid 32 Output

Transaction Stream/Channel ID

TID[31:0]:

Stream and Channel ID for Packet 0 (Both Single Packet Mode and Multi Packet Mode) and Packet 1 (Multi Packet Mode only)

  • TID[31:26] – Stream ID for packet 1
  • TID[25:16] – Channel ID for packet 1
  • TID[15:10] – Stream ID for packet 0
  • TID[9:0] – Channel ID for packet 0

Valid on every transfer of the packet
aes_ip_app_tx_tkeep 64 Output

1'b1 for data byte, 1'b0 for null byte

Note: This signal does not allow a null byte in the beginning or middle of the transfer. It is only applicable during the end of the transfer.
aes_ip_app_tx_tlast 1 Output Last, indicates end of transfer.
aes_ip_app_tx_tuser.algorithm_types 1 Output

Indicates AES or SM4 mode for the current clock cycle

  • 1: SM4
  • 0: AES
aes_ip_app_tx_tuser.encrypt_decrypt 1 Output

Indicates Encrypt or Decrypt mode for the current clock cycle

  • 1: decrypt
  • 0: encrypt
aes_ip_app_tx_tuser.key_128b_256b 1 Output

Indicates 128 bit key size or 256 bit key size mode for the current clock cycle

  • 0: 128 bit key size
  • 1: 256 bit key size
aes_ip_app_tx_tuser.pattern 4 Output

This is a 4-bit encoding for the Traffic Pattern types.

4'b 0010: MACsec
aes_ip_app_tx_tuser.mac_iv_tweak_en 1 Output Indicates the data fields carry an IV (or tweak for XTS) and at the output this field indicates the data contains the MAC.
aes_ip_app_tx_tuser.data_en 1 Output Field indicates that for a given pattern ID the data bits carry the raw data into the crypto cores
aes_ip_app_tx_tuser.key_en 1 Output Indicates the data carries the keys
aes_ip_app_tx_tuser.auth_tag 128 Output ICV field on decryption packet
aes_ip_app_tx_tuser.error_clear 1 Output When asserted the QHIP resets the internal error indicated by the profile ID and the channel ID associated with this clock to allow usage of this profile and channel again.
aes_ip_app_tx_tuser_last_segment<segment number> 1 Output

Packet segmentation boundary indication for higher bandwidth transfer.

  • aes_ip_app_tx_tuser_last_segment0
  • aes_ip_app_tx_tuser_last_segment1
  • aes_ip_app_tx_tuser_last_segment2
  • aes_ip_app_tx_tuser_last_segment3

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