MACsec Intel® FPGA IP User Guide

ID 736108
Date 6/26/2023
Public

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7.7. Clocking

The diagram below shows the MACsec ED clock domains. Each color on the diagram shows a separate clock domain. The clock domain for each logic block is listed in the table below.

Figure 35. Clocking Diagram
Table 62.  Clocking Parameters
Design Blocks IOPLL (150MHz) E/F-tile Transceiver Clock IOPLL (400MHz) IOPLL (600MHz)
MACsec IP (exclude CSR)     X  
MACsec IP CSR X      
CSR Configuration X      
E/F-tile   X    
AXI-ST Bridges   X    
Multi Interface Buffering Mux/Demux (Connect to E/F-tile) X X X  
ICA HIP X   X X
Multi Interface Buffering Mux/Demux (Connect to Pattern Generator/Checker) X   X  
Pattern Generator/Checker     X