MACsec Intel® FPGA IP User Guide

ID 736108
Date 6/26/2023

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7. MACsec Intel® FPGA IP Example Design

The block diagram below shows the MACsec IP design example.
Figure 31. MACsec IP Design Example

The IP GUI can generate (5) individual design examples. In order to generate one of the variants below, please select the following options for your project and IP parameter settings.

Table 60.  Available MACsec Design Example Variant
Design E-tile Device F-tile Device Number of TX Ports Number of TX + RX Ports Port Data Width Maximum Crypto Channels
1x25G AGFC023R25A2I2V AGID019R18A2E2V 1 2 64 16
2x25G AGFC023R25A2I2V AGID019R18A2E2V 2 4 64 32
4x25G AGIC035R39A1E2V 4 8 64 64
1x100G AGIC035R39A1E2V 1 2 256 16
1x200G TX Simplex AGIC035R39A1E2V 1 1 512 8