MACsec Intel® FPGA IP User Guide

ID 736108
Date 10/21/2022

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Document Table of Contents SmartNIC

In a typical SmartNIC application, the flow of data is as shown below:

PCIe (Host) > PCIe (FPGA) > Packet Processing Blocks > MACsec IP (FPGA) > User Logic > Transceiver (QSFP28)

The figure below shows the location of the MACsec IP within a SmartNIC system. The bandwidth which could be achieved with such a system is 200Gbps.

Figure 1. SmartNIC