MACsec Intel® FPGA IP User Guide

ID 736108
Date 10/21/2022
Public
Document Table of Contents

1.2.2.2. Ethernet Bridge + Inline MACsec

Inline Security Acceleration and Chip-to-Chip Channel Security between IDUs (Internal Distributed Unit)

The diagram below illustrates one example of lookaside MACsec encryption/decryption acceleration using Grand Ridge CPU and Agilex FPGA. The encrypted or decrypted traffic is offloaded from the Grand Ridge CPU to FPGA and the soft MACsec IP processes the packets and then sends it back to the CPU.

Figure 2. Ethernet Bridge + Inline MACsec


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