MACsec Intel® FPGA IP User Guide

ID 736108
Date 10/21/2022

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Document Table of Contents

6.6.1. Packet Aggregator

The Packet Aggregator is responsible for aggregating traffic from the Encryption/Decryption Framer into a single AES port with 512b data width. The Packet Aggregator consists of 2 input ports, one for handling transmit lane traffic and the other for handling receive lane traffic.

When the transmit or receive lanes first enter the Packet Aggregator, it is queued in each port FIFO respectively waiting for arbitration.

The transmit and receive lane traffic arbitrates between the 2 FIFOs in a round robin scheme and in every cycle each port is granted 64B depending on the Crypto HIP mode. If one of the FIFO is empty, the arbitration skips this FIFO and grants traffic on another FIFO.

Besides the AXI-ST TDATA signal, all TUSER signals are queued into the respective FIFOs and sent together with the packet data.

The Packet Aggregator supports the AXI-ST Multi-Packet Mode.