MACsec Intel® FPGA IP User Guide

ID 736108
Date 10/21/2022
Public

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6.1.2. AXI-ST Multi Packet Mode

The AXI-ST Multi Packet Mode is supported on all user interface input and output ports.

The waveform below shows the example of a two segment Multi-Packet mode implementation. Since the NUM_OF_SEG = 2, the 16 byte wide data bus is divided by 2 and each segment data bus width is 8 byte. If the NUM_OF_SOP = 2, then in this example, a new packet can start on byte 0 of segment 0 or byte 0 of segment 1 (i.e. byte 1 of the data bus) or BOTH for the same data transfer phase. If the NUM_OF_SOP = 1, then a new packet can start on byte 0 of segment 0 or byte 0 of segment 1 (but NOT BOTH) for the same data transfer phase.

Figure 26. Multi-Packet Mode