1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook
2.1. Creating Nios® V Processor System Design with Platform Designer
2.2. Integrating Platform Designer System into the Quartus® Prime Project
2.3. Designing a Nios® V Processor Memory System
2.4. Clocks and Resets Best Practices
2.5. Assigning a Default Agent
2.6. Assigning a UART Agent for Printing
2.7. JTAG Signals
2.8. Optimizing Platform Designer System Performance
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from On-Chip Flash (UFM)
4.6. Nios® V Processor Booting from General Purpose QSPI Flash
4.7. Nios® V Processor Booting from Configuration QSPI Flash
4.8. Nios® V Processor Booting from On-Chip Memory (OCRAM)
4.9. Nios® V Processor Booting from Tightly Coupled Memory (TCM)
4.10. Summary of Nios® V Processor Vector Configuration and BSP Settings
4.11. Reducing Nios® V Processor Booting Time
4.7.3.1.1. Hardware Design Flow
4.7.3.1.2. Software Design Flow
4.7.3.1.3. Software Design Flow (Bootloader via SDM Project)
4.7.3.1.4. Software Design Flow (User Application Project)
Creating the User Application BSP Project
Configure BSP Editor and Generate the BSP Project
Creating the User Application Project
Building the Application Project
Generating the HEX File
4.7.3.1.5. Programming Files Generation
4.7.3.1.6. QSPI Flash Programming SDM
6.2.3.2.1. Enabling Signal Tap Logic Analyzer
6.2.3.2.2. Adding Signals for Monitoring and Debugging
6.2.3.2.3. Specifying Trigger Conditions
6.2.3.2.4. Assigning the Acquisition Clock, Sample Depth, and Memory Type, and Buffer Acquisition Mode
6.2.3.2.5. Compiling the Design and Programming the Target Device
6.6.1. Prerequisites
6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.6.3. Creating Nios V Processor Software
6.6.4. Generating Memory Initialization File
6.6.5. Generating System Simulation Files
6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
4.7.3.1.4. Software Design Flow (User Application Project)
This section provides the design flow to generate and build the Nios® V processor user application.
Creating the User Application BSP Project
To launch the BSP Editor, follow these steps:
- In the Platform Designer window, select File > New BSP . The Create New BSP windows appears.
- For BSP setting file, navigate to the software/user_application/bsp folder and name the BSP as settings.bsp.
BSP path: <project directory>/software/user_application/bsp/settings.bsp
- For System file (qsys or sopcinfo), select the Nios® V processor Platform Designer system (.qsys).
- For Quartus project, select the Quartus Project File.
- For Revision, select the correct revision.
- For CPU name, select the Nios® V processor.
- Select the Operating system as Altera HAL.
- Click Create to create the BSP file.
Figure 142. Create New BSP Window
Configure BSP Editor and Generate the BSP Project
- Go to Main > Settings > Settings > Advanced > hal.linker.
- Enable the following settings:
- enable_alt_load
- enable_alt_load_copy_exceptions
Figure 143. hal.linker Settings - Click the BSP Linker Script tab in the BSP Editor.
Figure 144. Linker Region Settings
- Set all the Linker Section Name list to the User Application RAM.
- Click Generate BSP. Make sure the BSP generation is successful.
- Close the BSP Editor.
Creating the User Application Project
- Navigate to the software/user_application/app folder and create your user application source code.
- Launch the Nios V Command Shell.
- Execute the command below to generate the user application CMakeLists.txt.
niosv-app --app-dir=software/user_application/app \ --bsp-dir=software/user_application/bsp \ --srcs=software/user_application/app/<user application>
Building the Application Project
You can choose to build the application project using the RiscFree* IDE for Altera FPGAs or through the command line interface (CLI).
With the CLI, you can build the user application using the following commands:
cmake -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=Debug \ -B software/user_application/app/debug -S software/user_application/app
make -C software/user_application/app/debug
The user application (.elf) file is created in software/user_application/app/debug folder.
Generating the HEX File
You must generate a .hex file from your application .elf file, so you can create a .jic file suitable for programming flash devices.
- Launch the Nios V Command Shell.
- For Nios® V processor application copied from QSPI flash using bootloader via SDM, use the following commands to convert the ELF to HEX for your application. These commands creates the user application (.hex) file.
elf2flash --input software/user_application/app/debug/<user application>.elf \ --output flash.srec –epcs –-offset 0x0
riscv32-unknown-elf-objcopy --input-target srec \ --output-target ihex flash.srec \ <user application>.hex
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