Nios® V Embedded Processor Design Handbook

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ID 726952
Date 12/09/2025
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Document Table of Contents
Document Table of Contents x
1. About the Nios® V Embedded Processor 2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer 3. Nios® V Processor Software System Design 4. Nios® V Processor Debugging, Verifying, and Simulating 5. Nios® V Processor Configuration and Booting Solutions 6. Finding Nios® V Processor Design Example 7. Nios® V Processor - Using the MicroC/TCP-IP Stack 8. Nios® V Processor — Remote System Update 9. Nios® V Processor — Using Custom Instruction 10. Nios® V Processor – Running TinyML Application 11. Nios® V Processor – Implementing Lockstep Capabilities 12. Nios® V Embedded Processor Design Handbook Archives 13. Document Revision History for the Nios® V Embedded Processor Design Handbook
1. About the Nios® V Embedded Processor x
1.1. Altera® FPGA and Embedded Processors Overview 1.2. Quartus® Prime Software Support 1.3. Nios® V Processor Licensing 1.4. Embedded System Design 1.5. Recommended Tools from Quartus® Prime Installer
1.5. Recommended Tools from Quartus® Prime Installer x
1.5.1. Embedded FPGA Hardware and Software Developer 1.5.2. Embedded FPGA Hardware Developer 1.5.3. Embedded FPGA Software Developer
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer x
2.1. Creating Nios® V Processor System Design with Platform Designer 2.2. Clocks and Resets Best Practices 2.3. Designing a Nios® V Processor Memory System 2.4. Assigning a UART Agent for Printing 2.5. Assigning a Default Agent 2.6. Understanding the Design Requirement with JTAG Signals 2.7. Optimizing Platform Designer System Performance 2.8. Integrating Platform Designer System into the Quartus® Prime Project 2.9. Handing Off to an Embedded FPGA Software Developer
2.1. Creating Nios® V Processor System Design with Platform Designer x
2.1.1. Instantiating Nios® V Processor Altera® FPGA IP 2.1.2. Defining System Component Design 2.1.3. Specifying Base Addresses and Interrupt Request Priorities
2.1.1. Instantiating Nios® V Processor Altera® FPGA IP x
2.1.1.1. Instantiating Nios® V/c Compact Microcontroller Altera® FPGA IP 2.1.1.2. Instantiating Nios® V/m Microcontroller Altera® FPGA IP 2.1.1.3. Instantiating Nios® V/g General Purpose Processor Altera® FPGA IP
2.1.1.1. Instantiating Nios® V/c Compact Microcontroller Altera® FPGA IP x
2.1.1.1.1. CPU Architecture Tab 2.1.1.1.2. Use Reset Request Tab 2.1.1.1.3. Traps, Exceptions, and Interrupts Tab 2.1.1.1.4. ECC Tab
2.1.1.2. Instantiating Nios® V/m Microcontroller Altera® FPGA IP x
2.1.1.2.1. Debug Tab 2.1.1.2.2. Use Reset Request Tab 2.1.1.2.3. Traps, Exceptions, and Interrupts Tab 2.1.1.2.4. CPU Architecture 2.1.1.2.5. ECC Tab
2.1.1.3. Instantiating Nios® V/g General Purpose Processor Altera® FPGA IP x
2.1.1.3.1. CPU Architecture 2.1.1.3.2. Debug Tab 2.1.1.3.3. Lockstep Tab 2.1.1.3.4. Use Reset Request Tab 2.1.1.3.5. Traps, Exceptions, and Interrupts Tab 2.1.1.3.6. Memory Configurations Tab 2.1.1.3.7. ECC Tab 2.1.1.3.8. Custom Instruction Tab
2.2. Clocks and Resets Best Practices x
2.2.1. System JTAG Clock 2.2.2. Reset Request Interface 2.2.3. Reset Release IP
2.2.2. Reset Request Interface x
2.2.2.1. Typical Use Cases
2.3. Designing a Nios® V Processor Memory System x
2.3.1. Volatile Memory 2.3.2. Non-Volatile Memory
2.3.1. Volatile Memory x
2.3.1.1. On-Chip Memory Configuration – RAM or ROM 2.3.1.2. Caches 2.3.1.3. Tightly Coupled Memory 2.3.1.4. External Memory Interface (EMIF)
2.3.1.2. Caches x
2.3.1.2.1. Peripheral region
2.3.1.4. External Memory Interface (EMIF) x
2.3.1.4.1. Address Span Extender IP 2.3.1.4.2. Using Address Span Extender IP with Nios® V Processor 2.3.1.4.3. Defining Address Span Extender Linker Memory Device
2.4. Assigning a UART Agent for Printing x
2.4.1. Preventing Stalls by the JTAG UART
2.8. Integrating Platform Designer System into the Quartus® Prime Project x
2.8.1. Instantiating the Nios® V Processor System Module in the Quartus® Prime Project 2.8.2. Connecting Signals and Assigning Physical Pin Locations 2.8.3. Constraining the Altera FPGA Design
3. Nios® V Processor Software System Design x
3.1. Receiving from Embedded FPGA Hardware Developer 3.2. Nios V Processor Software Development Flow 3.3. Altera FPGA Embedded Development Tools
3.2. Nios V Processor Software Development Flow x
3.2.1. Board Support Package Project 3.2.2. Application Project
3.3. Altera FPGA Embedded Development Tools x
3.3.1. Nios® V Processor Board Support Package Editor 3.3.2. RiscFree* IDE for Altera FPGAs 3.3.3. Nios V Utilities Tools 3.3.4. File Format Conversion Tools 3.3.5. Other Utilities Tools
4. Nios® V Processor Debugging, Verifying, and Simulating x
4.1. Debugging Nios® V/c Processor 4.2. Debugging Nios® V Processor Hardware Designs 4.3. Debugging Nios® V Processor Software Designs 4.4. Debugging Tools 4.5. Additional Embedded Design Considerations 4.6. Simulating Nios® V Processor Designs
4.1. Debugging Nios® V/c Processor x
4.1.1. Pilot System with Non-pipelined Nios® V/m Processor 4.1.2. printf() Debugging
4.2. Debugging Nios® V Processor Hardware Designs x
4.2.1. JTAG Server 4.2.2. System Console 4.2.3. Signal Tap Logic Analyzer with Nios® V Processor Signal Tap Plugin 4.2.4. In-System Sources and Probes
4.2.2. System Console x
4.2.2.1. JTAG to Avalon® Host Bridge Core
4.2.3. Signal Tap Logic Analyzer with Nios® V Processor Signal Tap Plugin x
4.2.3.1. Hardware and Software Requirements 4.2.3.2. Setting Up Signal Tap Logic Analyzer 4.2.3.3. Running the Capture Session 4.2.3.4. Analyzing Results
4.2.3.2. Setting Up Signal Tap Logic Analyzer x
4.2.3.2.1. Enabling Signal Tap Logic Analyzer 4.2.3.2.2. Adding Signals for Monitoring and Debugging 4.2.3.2.3. Specifying Trigger Conditions 4.2.3.2.4. Assigning the Acquisition Clock, Sample Depth, and Memory Type, and Buffer Acquisition Mode 4.2.3.2.5. Compiling the Design and Programming the Target Device
4.2.3.2.3. Specifying Trigger Conditions x
4.2.3.2.3.1. Basic Trigger Conditions 4.2.3.2.3.2. Power-Up Trigger Conditions 4.2.3.2.3.3. Other Trigger Conditions 4.2.3.2.3.4. No Trigger Conditions
4.2.3.3. Running the Capture Session x
4.2.3.3.1. Performing Data Capture with Ashling* RiscFree* IDE for Altera® FPGAs 4.2.3.3.2. Performing Data Capture Without Software Download
4.2.3.4. Analyzing Results x
4.2.3.4.1. Viewing Data 4.2.3.4.2. Correlating Trace Data to Software ELF 4.2.3.4.3. Saving and Converting Captured Data
4.3. Debugging Nios® V Processor Software Designs x
4.3.1. Ashling* RiscFree* IDE for Altera™ FPGAs 4.3.2. Ashling Visual Studio Code Extension for Altera FPGAs 4.3.3. OpenOCD 4.3.4. Objdump File 4.3.5. Show Make Commands
4.5. Additional Embedded Design Considerations x
4.5.1. JTAG Signal Integrity 4.5.2. Additional Memory Space for System Prototyping
4.6. Simulating Nios® V Processor Designs x
4.6.1. Prerequisites 4.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer 4.6.3. Creating Nios V Processor Software 4.6.4. Generating Memory Initialization File 4.6.5. Generating System Simulation Files 4.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
4.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer x
4.6.2.1. Using IP and Platform Designer Simulation Setup Scripts
4.6.3. Creating Nios V Processor Software x
4.6.3.1. Generating the Board Support Package 4.6.3.2. Generating the Application Project File 4.6.3.3. Building the Application Project
5. Nios® V Processor Configuration and Booting Solutions x
5.1. Introduction 5.2. Linking Applications 5.3. Nios® V Processor Booting Methods 5.4. Introduction to Nios® V Processor Booting Methods 5.5. Nios® V Processor Booting from On-Chip Flash (UFM) 5.6. Nios® V Processor Booting from General Purpose QSPI Flash 5.7. Nios® V Processor Booting from Configuration QSPI Flash 5.8. Nios® V Processor Booting from On-Chip Memory (OCRAM) 5.9. Nios® V Processor Booting from Tightly Coupled Memory (TCM) 5.10. Summary of Nios® V Processor Vector Configuration and BSP Settings 5.11. Reducing Nios® V Processor Booting Time
5.2. Linking Applications x
5.2.1. Linking Behavior
5.2.1. Linking Behavior x
5.2.1.1. Default BSP Linking 5.2.1.2. Configurable BSP Linking
5.4. Introduction to Nios® V Processor Booting Methods x
5.4.1. Nios® V Processor Application Execute-In-Place from Boot Flash 5.4.2. Nios® V Processor Application Copied from Boot Flash to RAM Using Boot Copier 5.4.3. Nios® V Processor Application Execute-In-Place from OCRAM 5.4.4. Nios® V Processor Application Execute-In-Place from TCM
5.4.1. Nios® V Processor Application Execute-In-Place from Boot Flash x
5.4.1.1. alt_load()
5.4.2. Nios® V Processor Application Copied from Boot Flash to RAM Using Boot Copier x
5.4.2.1. Nios® V Processor Bootloader via Generic Serial Flash Interface 5.4.2.2. Nios® V Processor Bootloader via Secure Device Manager
5.5. Nios® V Processor Booting from On-Chip Flash (UFM) x
5.5.1. MAX® 10 FPGA On-Chip Flash Description 5.5.2. Nios® V Processor Application Execute-In-Place from UFM 5.5.3. Nios® V Processor Application Copied from UFM to RAM using Boot Copier
5.5.2. Nios® V Processor Application Execute-In-Place from UFM x
5.5.2.1. Hardware Design Flow 5.5.2.2. Software Design Flow 5.5.2.3. Programming
5.5.3. Nios® V Processor Application Copied from UFM to RAM using Boot Copier x
5.5.3.1. Hardware Design Flow 5.5.3.2. Software Design Flow 5.5.3.3. Programming
5.6. Nios® V Processor Booting from General Purpose QSPI Flash x
5.6.1. Nios® V Processor Application Executes-In-Place from General Purpose QSPI Flash 5.6.2. Nios® V Processor Application Copied from General Purpose QSPI Flash to RAM Using Boot Copier (Bootloader via GSFI)
5.6.1. Nios® V Processor Application Executes-In-Place from General Purpose QSPI Flash x
5.6.1.1. Hardware Design Flow 5.6.1.2. Software Design Flow 5.6.1.3. Programming Files Generation 5.6.1.4. QSPI Flash Programming
5.6.2. Nios® V Processor Application Copied from General Purpose QSPI Flash to RAM Using Boot Copier (Bootloader via GSFI) x
5.6.2.1. Hardware Design Flow 5.6.2.2. Software Design Flow 5.6.2.3. Programming Files Generation 5.6.2.4. QSPI Flash Programming
5.7. Nios® V Processor Booting from Configuration QSPI Flash x
5.7.1. Nios V Processor Design, Configuration and Boot Flow (Control Block-based Device) 5.7.2. Nios V Processor Design, Configuration and Boot Flow (SDM-based Devices)
5.7.1. Nios V Processor Design, Configuration and Boot Flow (Control Block-based Device) x
5.7.1.1. Nios® V Processor Application Executes-In-Place from Configuration QSPI Flash 5.7.1.2. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (Bootloader via GSFI) 5.7.1.3. Bootloader via GSFI Example Design
5.7.1.1. Nios® V Processor Application Executes-In-Place from Configuration QSPI Flash x
5.7.1.1.1. Hardware Design Flow 5.7.1.1.2. Software Design Flow 5.7.1.1.3. Programming Files Generation 5.7.1.1.4. QSPI Flash Programming
5.7.1.2. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (Bootloader via GSFI) x
5.7.1.2.1. Hardware Design Flow 5.7.1.2.2. Software Design Flow 5.7.1.2.3. Programming Files Generation 5.7.1.2.4. QSPI Flash Programming
5.7.2. Nios V Processor Design, Configuration and Boot Flow (SDM-based Devices) x
5.7.2.1. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (Bootloader via SDM) 5.7.2.2. Bootloader via SDM Example Design
5.7.2.1. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (Bootloader via SDM) x
5.7.2.1.1. Hardware Design Flow 5.7.2.1.2. Software Design Flow 5.7.2.1.3. Software Design Flow (Bootloader via SDM Project) 5.7.2.1.4. Software Design Flow (User Application Project) 5.7.2.1.5. Programming Files Generation 5.7.2.1.6. QSPI Flash Programming SDM
5.8. Nios® V Processor Booting from On-Chip Memory (OCRAM) x
5.8.1. Nios® V Processor Application Executes in-place from OCRAM
5.8.1. Nios® V Processor Application Executes in-place from OCRAM x
5.8.1.1. Hardware Design Flow 5.8.1.2. Software Design Flow 5.8.1.3. Programming
5.9. Nios® V Processor Booting from Tightly Coupled Memory (TCM) x
5.9.1. Nios® V Processor Application Executes in-place from TCM
5.9.1. Nios® V Processor Application Executes in-place from TCM x
5.9.1.1. Hardware Design Flow 5.9.1.2. Software Design Flow 5.9.1.3. Programming
5.11. Reducing Nios® V Processor Booting Time x
5.11.1. Boot Methods 5.11.2. Boot devices 5.11.3. Peripheral Initialization 5.11.4. Caches 5.11.5. System Speed
6. Finding Nios® V Processor Design Example x
6.1. Altera FPGA Developer Site 6.2. FPGA Design Store
7. Nios® V Processor - Using the MicroC/TCP-IP Stack x
7.1. Introduction 7.2. Software Architecture 7.3. Support and Licensing 7.4. MicroC/TCP-IP Example Designs 7.5. Development Flow 7.6. Operating the Example Designs 7.7. Optional Configuration 7.8. MicroC/TCP-IP Simple Socket Server Concepts
7.4. MicroC/TCP-IP Example Designs x
7.4.1. Hardware and Software Requirements 7.4.2. Overview 7.4.3. Acquiring the Example Design Files 7.4.4. Hardware Design Files 7.4.5. Software Design Files
7.4.5. Software Design Files x
7.4.5.1. MicroC/TCP-IP IPerf Example Design 7.4.5.2. MicroC/TCP-IP Simple Socket Server Example Design
7.5. Development Flow x
7.5.1. Hardware Development Flow 7.5.2. Software Development Flow 7.5.3. Device Programming
7.5.2. Software Development Flow x
7.5.2.1. Creating a BSP project 7.5.2.2. Configuring the BSP 7.5.2.3. Creating an Application Project 7.5.2.4. Building the Application Project
7.6. Operating the Example Designs x
7.6.1. Operating the MicroC/TCP-IP IPerf 7.6.2. Operating the MicroC/TCP-IP Simple Socket Server
7.7. Optional Configuration x
7.7.1. Configuring Hardware Name 7.7.2. Configuring MAC and IP Addresses 7.7.3. Configuring MicroC/TCP-IP Initialization 7.7.4. Configuring iPerf Server Auto-Initialization
7.7.3. Configuring MicroC/TCP-IP Initialization x
7.7.3.1. Network Task Configuration 7.7.3.2. Network Interface Configuration
7.8. MicroC/TCP-IP Simple Socket Server Concepts x
7.8.1. MicroC/OS-II Resources 7.8.2. Error Handling 7.8.3. MicroC/TCP-IP Stack Default Configuration
8. Nios® V Processor — Remote System Update x
8.1. Overview 8.2. Quartus® Prime Pro Edition Software and Tool Support 8.3. Nios® V Processor RSU Quick Start Guide in SDM-based Devices
8.2. Quartus® Prime Pro Edition Software and Tool Support x
8.2.1. Quartus® Prime Pro Edition Software 8.2.2. Programming File Generator
8.2.1. Quartus® Prime Pro Edition Software x
8.2.1.1. Setting Max Retry Parameter 8.2.1.2. Selecting Factory Load Pin
8.2.2. Programming File Generator x
8.2.2.1. Programming File Generator File Types 8.2.2.2. Bitswap Option 8.2.2.3. Quartus® Prime Programmer 8.2.2.4. Supported QSPI Flash Devices
8.3. Nios® V Processor RSU Quick Start Guide in SDM-based Devices x
8.3.1. Individual Factory, Application, and Update Images 8.3.2. Hardware Design Flow 8.3.3. Software Design Flow 8.3.4. Individual Images Generation 8.3.5. Remote System Update Image Files Generation 8.3.6. QSPI Flash Programming 8.3.7. Operating the RSU Client API
8.3.2. Hardware Design Flow x
8.3.2.1. Create a Platform Designer System 8.3.2.2. Quartus® Prime Software Settings
8.3.3. Software Design Flow x
8.3.3.1. Generating the ZLIB libraries 8.3.3.2. Creating a Board Support Package Project 8.3.3.3. Configuring and Generating the BSP Project 8.3.3.4. Creating Multiple Application Projects 8.3.3.5. Building the Application Projects 8.3.3.6. Generating HEX Files
8.3.5. Remote System Update Image Files Generation x
8.3.5.1. Generating Initial RSU Image Using SOF file 8.3.5.2. Generating an Application Update Image 8.3.5.3. Generating a Factory Update Flash Image
8.3.6. QSPI Flash Programming x
8.3.6.1. Programming the Initial RSU Image 8.3.6.2. Programming the Update Images
8.3.7. Operating the RSU Client API x
8.3.7.1. Trigger Reconfiguration Menu with Selected Image 8.3.7.2. Updating an Application Image 8.3.7.3. Updating the Factory Image
9. Nios® V Processor — Using Custom Instruction x
9.1. Introduction 9.2. Unimplemented Instruction Example Design 9.3. Hardware Acceleration Example Design
9.2. Unimplemented Instruction Example Design x
9.2.1. Hardware and Software Requirements 9.2.2. Overview 9.2.3. Acquiring the Example Design File 9.2.4. Hardware Design Files 9.2.5. Software Design Files 9.2.6. Development Flow 9.2.7. Operating the Example Design
9.2.6. Development Flow x
9.2.6.1. Hardware Development Flow 9.2.6.2. Software Development Flow 9.2.6.3. Device Programming
9.3. Hardware Acceleration Example Design x
9.3.1. Hardware and Software Requirements 9.3.2. Overview 9.3.3. Acquiring the Example Design File 9.3.4. Hardware Design Files 9.3.5. Software Design Files 9.3.6. Development Flow 9.3.7. Operating the Example Design
9.3.6. Development Flow x
9.3.6.1. Hardware Development Flow 9.3.6.2. Software Development Flow 9.3.6.3. Device Programming
1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Debugging, Verifying, and Simulating
5. Nios® V Processor Configuration and Booting Solutions
6. Finding Nios® V Processor Design Example
7. Nios® V Processor - Using the MicroC/TCP-IP Stack
8. Nios® V Processor — Remote System Update
9. Nios® V Processor — Using Custom Instruction
10. Nios® V Processor – Running TinyML Application
11. Nios® V Processor – Implementing Lockstep Capabilities
12. Nios® V Embedded Processor Design Handbook Archives
13. Document Revision History for the Nios® V Embedded Processor Design Handbook

2.3.1.2.1. Peripheral region

Cache is highly recommended for external memories which are affected by long access time, while internal on-chip memories may be excluded due to their short access time. You must not cache any embedded peripheral IPs, such as UART, I2C, and SPI, except for memories. Caching an embedded peripheral can lead to issues due to potential anomalies:
  1. Delayed/Missed Writes - When the processor writes a command to a peripheral's memory address, the data might only be updated in the cache, not the actual physical register of the peripheral itself. The peripheral holds the old value, therefor, the command is never executed.
  2. Stale Reads - When the processor reads a status register from a peripheral (e.g., to check if a task is complete or a sensor value), the cache might return a previously cached, stale value instead of fetching the fresh data from the physical register.
  3. Cache Coherency Issues (with DMA) - Direct Memory Access (DMA) controllers move data directly to or from main memory, bypassing the cache. If the processor tries to access that data from a cached memory location, it could read an outdated copy from its cache, not the new data the DMA controller just wrote to RAM.

In summary, the memory-mapped region of embedded peripheral IPs is uncacheable and must reside within the processor’s peripheral regions.

To set a peripheral region, follow these steps:
  1. Open the system’s Address Map in the Platform Designer.
  2. Navigate to the address map of the processor’s Instruction Manager and Data Manager.
  3. Identify the peripherals and memories in your system.
    Figure 14. Example of Address Map
    Note: The blue arrows are pointing to memories.
  4. Group the peripherals:
    1. Memory as cacheable
    2. Peripherals as uncacheable
    Table 24.  Cacheable and Uncacheable Region
    Subordinate Address Map Status Peripheral Region
    Size Base Address
    user_application_mem.s1 0x0 ~ 0x3ffff Cacheable N/A N/A
    cpu.dm_agent 0x40000 ~ 0x4ffff Uncacheable 65536 bytes 0x40000
    bootcopier_rom.s1 0x50000 ~ 0x517ff Cacheable N/A N/A
    bootcopier_ram.s1 0x52000 ~ 0x537ff Cacheable
    cpu.timer_sw_agent 0x54000 ~ 0x5403f Uncacheable

    144 bytes

    (min size is 65536 bytes)

    		 0x54000
    mailbox.avmm 0x54040 ~ 0x5407f Uncacheable
    sysid_qsys_0.control_slave 0x54080 ~ 0x54087 Uncacheable
    uart.avalon_jtag_slave 0x54088 ~ 0x5408f Uncacheable
  5. Align the peripheral regions with their specific sizes:
    • For example, if the size is 65536 bytes, it corresponds to 0x10000 bytes. Therefore, the allowed base address must be a multiple of 0x10000.
    • The CPU.dm_agent uses a base address of 0x40000, which is a multiple of 0x10000. As a result, Peripheral Region A, with a size of 65536 bytes and a base address of 0x40000, meets the requirements.
    • The base address of the collection of uncacheable regions at 0x54000 is not a multiple of 0x10000. You must reassign them to 0x60000 or other multiple of 0x10000. Thus, Peripheral Region B, which has a size of 65536 bytes and a base address of 0x60000, satisfies the criteria.
Table 25.  Cacheable and Uncacheable Region with Reassignment
Subordinate Address Map Status Peripheral Region
Size Base Address
user_application_mem.s1 0x0 ~ 0x3ffff Cacheable N/A N/A
cpu.dm_agent 0x40000 ~ 0x4ffff Uncacheable 65536 bytes 0x40000
bootcopier_rom.s1 0x50000 ~ 0x517ff Cacheable N/A N/A
bootcopier_ram.s1 0x52000 ~ 0x537ff Cacheable
cpu.timer_sw_agent 0x60000 ~ 0x6003f Uncacheable

144 bytes

(min size is 65536 bytes)

 0x60000
mailbox.avmm 0x60040 ~ 0x6007f Uncacheable
sysid_qsys_0.control_slave 0x60080 ~ 0x60087 Uncacheable
uart.avalon_jtag_slave 0x60088 ~ 0x6008f Uncacheable
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