F-Tile Ethernet Multirate Intel® FPGA IP User Guide

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ID 714307
Date 6/20/2022
Public

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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide
1. Introduction x
1.1. Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation 1.7. F-Tile Ethernet Multirate IP Core Features and Constraints 1.8. F-Tile Ethernet Multirate IP Core Concepts
1.8. F-Tile Ethernet Multirate IP Core Concepts x
1.8.1. Reconfiguration Group 1.8.2. Base Profile 1.8.3. Secondary Profile 1.8.4. Secondary Profile Group 1.8.5. Startup Profile 1.8.6. Supported Reconfiguration Groups 1.8.7. PTP Timestamp Accuracy Support 1.8.8. Transceiver Lane Mapping
2. Interface Overview x
2.1. Port Numbering Scheme 2.2. Clock Signals 2.3. Reset Signals 2.4. Fractured MAC Segmented Interface for FGT Transceivers 2.5. Fractured MAC SOP-Aligned Client Interface for FGT Transceivers 2.6. Fractured MII or PCS-Only Interface for FGT Transceivers 2.7. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers 2.8. MAC Flow Control Interface 2.9. Status Interface 2.10. Avalon® Memory-Mapped Reconfiguration Interfaces 2.11. Precision Time Protocol Interface
2.11. Precision Time Protocol Interface x
2.11.1. PTP Clock Interface 2.11.2. Time-of-Day Interface 2.11.3. TX 2-Step Timestamp Interface 2.11.4. TX 1-Step Timestamp Interface 2.11.5. RX Timestamp Interface 2.11.6. PTP Status Interface 2.11.7. PTP Tile Interface
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Precision Time Protocol
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide

1.8.7. PTP Timestamp Accuracy Support

The table below specifies the PTP timestamp accuracy modes supported per profile within each reconfiguration group. Mixture of Basic and Advanced accuracy modes is not supported. If you plan to use a secondary profile that does not support advanced accuracy mode, you must set the timestamp accuracy to Basic.
Supported Timestamp Accuracy Modes per Profile
Reconfiguration Group Base and Supported Secondary Profiles Supported Timestamp Accuracy Mode
25GE-1 Reconfigurable 1x25GE Basic, Advanced
1x10GE Basic, Advanced
50GE-1 Reconfigurable 1x50GE-1 Basic, Advanced
1x25GE-1 Basic, Advanced
1x10GE -1 Basic, Advanced
100GE-4 Reconfigurable 1x100GE-4 Basic, Advanced
2x50GE-2 Basic, Advanced
1x100GE-2 Basic, Advanced
4x25GE-1 Basic, Advanced
4x10GE-1 Basic, Advanced
2x50GE-1 Basic
100GE-2 Reconfigurable 1x100GE-2 Basic, Advanced
2x50GE-1 Basic, Advanced
2x25GE-1 Basic, Advanced
2x10GE-1 Basic, Advanced
1x50GE-2 Basic
400GE-8 Reconfigurable 1x400GE-8 Basic, Advanced
2x200GE-4 Basic, Advanced
4x100GE-2 Basic, Advanced
200GE-4 Reconfigurable 1x200GE-4 Basic, Advanced
2x100GE-2 Basic, Advanced
1x100GE-4 Basic
2x50GE-2 Basic
4x50GE-1 Basic, Advanced
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