F-Tile Ethernet Multirate Intel® FPGA IP User Guide

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ID 714307
Date 6/20/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide
1. Introduction x
1.1. Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation 1.7. F-Tile Ethernet Multirate IP Core Features and Constraints 1.8. F-Tile Ethernet Multirate IP Core Concepts
1.8. F-Tile Ethernet Multirate IP Core Concepts x
1.8.1. Reconfiguration Group 1.8.2. Base Profile 1.8.3. Secondary Profile 1.8.4. Secondary Profile Group 1.8.5. Startup Profile 1.8.6. Supported Reconfiguration Groups 1.8.7. PTP Timestamp Accuracy Support 1.8.8. Transceiver Lane Mapping
2. Interface Overview x
2.1. Port Numbering Scheme 2.2. Clock Signals 2.3. Reset Signals 2.4. Fractured MAC Segmented Interface for FGT Transceivers 2.5. Fractured MAC SOP-Aligned Client Interface for FGT Transceivers 2.6. Fractured MII or PCS-Only Interface for FGT Transceivers 2.7. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers 2.8. MAC Flow Control Interface 2.9. Status Interface 2.10. Avalon® Memory-Mapped Reconfiguration Interfaces 2.11. Precision Time Protocol Interface
2.11. Precision Time Protocol Interface x
2.11.1. PTP Clock Interface 2.11.2. Time-of-Day Interface 2.11.3. TX 2-Step Timestamp Interface 2.11.4. TX 1-Step Timestamp Interface 2.11.5. RX Timestamp Interface 2.11.6. PTP Status Interface 2.11.7. PTP Tile Interface
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Precision Time Protocol
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide

2.2. Clock Signals

This section describes required clock connections and clock signals for the F-Tile Ethernet Multirate IP core.

The Ethernet Multirate IP core uses the o_clk_pll common system PLL clock for all ports within a reconfiguration group.

The i_reconfig_clk input is a common clock for the Avalon® memory-mapped interfaces of all ports within a reconfiguration group. You must use the same reconfiguration clock in the F-Tile Dynamic Reconfiguration IP core and all F-Tile Ethernet Multirate IP core instances targeting a particular tile.

You must make the following clock connections:
  • The i_clk_ref and the i_clk_sys clocks drives the IP core.
  • The output clock o_clk_pll drives both the i_clk_rx and the i_clk_tx input signals.
Figure 3. Typical Clock ConnectionsThis diagram displays Ethernet Multirate IP core and its related clock signals.
Table 11.  Clock SignalsThis table lists the common input clock signals for the Ethernet Multirate IP core.
Signal Name Number of Ports I/O Direction Description
Clock Inputs
i_clk_tx 1, 2, or 4 Input TX datapath clock

This clock drives the active TX interface for the port.

This clock source is:
  • o_clk_pll clock unless you enabled Enable asynchronous adapter clocks parameter
  • o_clk_pll of the PTP tile adapter when Enable IEEE 1588 PTP parameter is enabled
i_clk_rx 1, 2, or 4 Input RX datapath clock

This clock drives the active RX interface for the port.

This clock source is:
  • o_clk_pll clock unless you enabled Enable asynchronous adapter clocks parameter
  • o_clk_pll of the PTP tile adapter when Enable IEEE 1588 PTP parameter is enabled
i_reconfig_clk 1, 2, or 4 Input Avalon® memory-mapped interface reconfiguration clock

The interface uses this clock to access control status registers (CSRs). The clock supports 100 to 250 MHz frequency.

When PTP is enabled, the i_reconfig_clk frequency supports the range of 100 to 250 MHz.

i_clk_ref 1, 2, or 4 Input PMA reference clock
F-Tile Reference and System PLL Clock Intel® FPGA IP drives this clock.
  • 312.5 MHz when using FGT PMA without auto-negotiation and link training
  • 322.265625 MHz when using FGT PMA without auto-negotiation and link training
The clock source depends on the PMA selection.
  • When using FGT PMA, the clock source is the out_refclk_fgt_i output signal from the F-Tile Reference and System PLL Clocks Intel® FPGA IP.

Unless the Custom cadence parameter is enabled, the clock must be PPM matched to the i_clk_sys clock.

i_clk_sys 1, 2, or 4 Input Ethernet system clock

F-Tile Reference and System PLL Clocks Intel® FPGA IP drives this clock.

Unless Custom cadence parameter is enabled, the clock frequency depends on the FEC type:
  • 805.6640625 MHz or higher for all Ethernet modes without FEC, or with IEEE 802.3 BASE-R Firecode (CL74), or IEEE 802.3 RS(528,514) (CL91)
  • 830.078125 MHz or higher for all Ethernet modes with IEEE 802.3 RS(544,514) (CL134), Ethernet Technology Consortium RS(272, 258)
  • 322.265625 MHz or higher is also supported for 10GE without PTP
You must specify this frequency in the F-Tile Ethernet Multirate Intel® FPGA IP System PLL frequency IP parameter and in the F-Tile Reference and System PLL Clocks Intel® FPGA IP Mode of system PLL IP parameter.
Note: The i_clk_sys is a virtual signal. In simulation, the signal displays as 0.

Connect to the out_systempll_clk_i signal from the F-Tile Reference and System PLL Clocks Intel® FPGA IP.

Clock Outputs
o_clk_pll 1, 2, or 4 Output System PLL clock

Clock derived from the F-Tile System PLL associated with the Ethernet IP port. The o_clk_pll frequency is equal to PLL frequency divided by 2. The following shows the o_clk_pll frequency unless you enabled custom system PLL frequency.

Supports the following frequencies:
  • 402.83203125 MHz or higher for all Ethernet modes without FEC, with IEEE 802.3 BASE-R Firecode (CL74), or IEEE 802.3 RS(528,514) (CL91). The system PLL must be of 805.6640625 MHz frequency or higher.
  • 415.0390625 MHz or higher for all Ethernet modes with IEEE 802.3 RS(544,514) (CL134), with Ethernet Technology Consortium RS(272, 258). The system PLL must be of 830.078125 MHz frequency or higher.
  • 161.1328125 MHz or higher for 10GE without enabled PTP. The system PLL must be of 322.265625 MHz frequency or higher.
  • Custom system PLL frequency divided by 2, if custom system PLL frequency is used
Table 12.  Divided Clock Outputs SignalsThis table lists the divided clock outputs for the Ethernet Multirate IP core. Each reconfiguration group has separate divided clock outputs.
Signal Name Number of Ports I/O Direction Description
o_p0_clk_tx_div 1, 2, or 4 Output
Supports the following frequencies:
  • 156.25 MHz for 10GE
  • 312.5 MHz for 40GE
  • 390.625 MHz for all other Ethernet modes

Clock recovered from the TX SERDES rate divided by either 33/66/68, depending on the FEC mode and Ethernet mode parameters. The o_clk_tx_div is equal to:

  • TX SERDES rate divided by 33 for 40GE.
  • TX SERDES rate divided by 66 when FEC mode parameter is set to one of the following:
    • None except for 40GE
    • IEEE 802.3 BASE-R Firecode (CL74)
    • IEEE 802.3 RS(528,514) (CL91)
  • TX SERDES rate divided by 68 when FEC mode parameter is set to one of the following:
    • IEEE 802.3 RS(544,514) (CL134)
    • Ethernet Technology Consortium RS(272, 258)
o_p0_clk_rec_div64 1, 2, or 4 Output
Supports the following frequencies:
  • 161.1328125 MHz ± 200 PPM for 10GE/40GE
  • 402.83203125 MHz ± 200 PPM for Ethernet modes without FEC (except 10GE and 40GE), with IEEE 802.3 BASE-R Firecode (CL74), and IEEE 802.3 RS(528,514) (CL91)
  • 415.0390625 MHz ± 200 PPM for Ethernet modes with IEEE 802.3 RS(544,514) (CL134) and Ethernet Technology Consortium RS(272, 258)

Clock derived from RX recovered clock, divided by 64.

o_p0_clk_rec_div 1, 2, or 4 Output
Supports the following frequencies:
  • 156.25 MHz ± 200PPM for 10GE
  • 312.50 MHz ± 200PPM for 40GE
  • 390.625 MHz ± 200PPM for all other Ethernet modes

Clock derived from the RX recovered clock divided by either 33/66/68, depending on the FEC mode parameter. The o_clk_rec_div is equal to:

  • RX SERDES rate divided by 33 for 40GE
  • RX SERDES rate divided by 66 when FEC mode parameter is set to one of the following:
    • None except for 40GE
    • IEEE 802.3 BASE-R Firecode (CL74)
    • IEEE 802.3 RS(528,514) (CL91)
  • RX SERDES rate divided by 68 when FEC mode parameter is set to one of the following:
    • IEEE 802.3 RS(544,514) (CL134)
    • Ethernet Technology Consortium RS(272, 258)
o_p1_clk_tx_div 2 or 4 Output Same as the o_p0_clk_tx_div signal description
o_p1_clk_rec_div64 2 or 4 Output Same as the o_p0_clk_rec_div64 signal description
o_p1_clk_rec_div 2 or 4 Output Same as the o_p0_clk_rec_div signal description
o_p2_clk_tx_div 4 Output Same as the o_p0_clk_tx_div signal description
o_p2_clk_rec_div64 4 Output Same as the o_p0_clk_rec_div64 signal description
o_p2_clk_rec_div 4 Output Same as the o_p0_clk_rec_div signal description
o_p3_clk_tx_div 4 Output Same as the o_p0_clk_tx_div signal description
o_p3_clk_rec_div64 4 Output Same as the o_p0_clk_rec_div64 signal description
o_p3_clk_rec_div 4 Output Same as the o_p0_clk_rec_div signal description

The locked status output is common since all ports in the reconfiguration group share the same system PLL clock. The transceiver PLL and RX CDR lock signals are port-specific dependent on the Number of Ports setting.

Table 13.  Clock Status SignalsThis table lists the clock status ports for the Ethernet Multirate IP core. Use these ports to hold the circuits that use clock sources from the IP core in reset until the PLLs driving the clocks are locked. All signals are asynchronous.
Signal Name Number of Ports I/O Direction Description
o_sys_pll_locked 1, 2, or 4 Output Indicates the locked system PLL.

Do not use the o_clk_pll clock until the o_sys_pll_locked clock is high.

o_p0_tx_pll_locked 1, 2, or 4 Output Indicates the TX PLL driving clock signal from the core is locked.

Do not use the o_clk_tx_div clock until the o_p0_tx_pll_locked clock is high.

o_p0_cdr_lock 1, 2, or 4 Output Indicates that the recovered clocks are locked to data.

Do not use the o_clk_rec_div64 or o_clk_rec_div clocks until the o_p0_cdr_lock clock is high.

o_p1_tx_pll_locked 2 or 4 Output If you set the number of ports to 2 or 4, indicates the TX PLL driving clock signal from the core port1 is locked.

Do not use the o_clk_tx_div clock until the o_p1_tx_pll_locked clock is high.

o_p1_cdr_lock 2 or 4 Output If you set the number of ports to 2 or 4, indicates that the recovered clocks from port 1 are locked to data.

Do not use the o_clk_rec_div64 or o_clk_rec_div clocks until the o_p1_cdr_lock clock is high.

o_p2_tx_pll_locked 4 Output If you set the number of ports to 4, indicates the TX PLL driving clock signal from the core port2 is locked.

Do not use the o_clk_tx_div clock until the o_p2_tx_pll_locked clock is high.

o_p2_cdr_lock 4 Output If you set the number of ports to 4, indicates that the recovered clocks from port 2 are locked to data.

Do not use the o_clk_rec_div64 or o_clk_rec_div clocks until the o_p2_cdr_lock clock is high.

o_p3_tx_pll_locked 4 Output If you set the number of ports to 4, indicates the TX PLL driving clock signal from the core port3 is locked.

Do not use the o_clk_tx_div clock until the o_p3_tx_pll_locked clock is high.

o_p3_cdr_lock 4 Output If you set the number of ports to 4, indicates that the recovered clocks from port 3 are locked to data.

Do not use the o_clk_rec_div64 or o_clk_rec_div clocks until the o_p3_cdr_lock clock is high.

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