F-Tile Ethernet Multirate Intel® FPGA IP User Guide

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ID 714307
Date 6/20/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide
1. Introduction x
1.1. Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation 1.7. F-Tile Ethernet Multirate IP Core Features and Constraints 1.8. F-Tile Ethernet Multirate IP Core Concepts
1.8. F-Tile Ethernet Multirate IP Core Concepts x
1.8.1. Reconfiguration Group 1.8.2. Base Profile 1.8.3. Secondary Profile 1.8.4. Secondary Profile Group 1.8.5. Startup Profile 1.8.6. Supported Reconfiguration Groups 1.8.7. PTP Timestamp Accuracy Support 1.8.8. Transceiver Lane Mapping
2. Interface Overview x
2.1. Port Numbering Scheme 2.2. Clock Signals 2.3. Reset Signals 2.4. Fractured MAC Segmented Interface for FGT Transceivers 2.5. Fractured MAC SOP-Aligned Client Interface for FGT Transceivers 2.6. Fractured MII or PCS-Only Interface for FGT Transceivers 2.7. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers 2.8. MAC Flow Control Interface 2.9. Status Interface 2.10. Avalon® Memory-Mapped Reconfiguration Interfaces 2.11. Precision Time Protocol Interface
2.11. Precision Time Protocol Interface x
2.11.1. PTP Clock Interface 2.11.2. Time-of-Day Interface 2.11.3. TX 2-Step Timestamp Interface 2.11.4. TX 1-Step Timestamp Interface 2.11.5. RX Timestamp Interface 2.11.6. PTP Status Interface 2.11.7. PTP Tile Interface
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Precision Time Protocol
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide

2.11. Precision Time Protocol Interface

The Precision Time Protocol (PTP) interface is available when you enable Enable IEEE 1588 PTP option in the PTP tab. When selected, the IP generates PTP based 1-step or 2-step TX and RX timestamps. The IP requires the IEEE 1588 96-bit time-of-day (TOD) input.
The table below depicts the interface details for different number of ports. Each port within a reconfiguration group supports a separate TOD clock.
Table 42.  Signals of the Precision Time Protocol (PTP) Interface

For signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.

Maximum Number of Ports Applicable Reconfiguration Groups Signal Name
1

25GE-1 Reconfigurable

50GE-1 Reconfigurable

i_clk_ptp_sample

Port 0:

i_p0_clk_tx_tod

i_p0_clk_rx_tod

2

100GE-2 Reconfigurable

i_clk_ptp_sample

Port 0:

i_p0_clk_tx_tod

i_p0_clk_rx_tod

Port 1:

i_p1_clk_tx_tod

i_p1_clk_rx_tod

4

100GE-4 Reconfigurable

400GE-8 Reconfigurable

200GE-4 Reconfigurable

i_clk_ptp_sample

Port 0:

i_p0_clk_tx_tod

i_p0_clk_rx_tod

Port 1:

i_p1_clk_tx_tod

i_p1_clk_rx_tod

Port 2:

i_p2_clk_tx_tod

i_p2_clk_rx_tod

Port 3:

i_p3_clk_tx_tod

i_p3_clk_rx_tod


Section Content
PTP Clock Interface
Time-of-Day Interface
TX 2-Step Timestamp Interface
TX 1-Step Timestamp Interface
RX Timestamp Interface
PTP Status Interface
PTP Tile Interface

Level Two Title