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2.1. Port Numbering Scheme
2.2. Clock Signals
2.3. Reset Signals
2.4. Fractured MAC Segmented Interface for FGT Transceivers
2.5. Fractured MAC SOP-Aligned Client Interface for FGT Transceivers
2.6. Fractured MII or PCS-Only Interface for FGT Transceivers
2.7. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers
2.8. MAC Flow Control Interface
2.9. Status Interface
2.10. Avalon® Memory-Mapped Reconfiguration Interfaces
2.11. Precision Time Protocol Interface
1.4. Device Speed Grade Support
The F-Tile Ethernet Multirate Intel® FPGA IP core supports the following speed grades for Intel® Agilex™ devices:
- Core speed grade: -1 or -2 or -3
Note: Intel recommends -1 or -2 core speed grades for IP core variation with PTP.
- Table: F-Tile FGT Transmitter and Receiver Data Rate Performance for Intel® Agilex™ Devices
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