Symmetric Cryptographic Accelerator Hard IP User Guide

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ID 714305
Date 11/28/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP 5. Block Description 6. Cryptographic IP Data Profiles 7. Configuration Registers 8. Design Example 9. Document Revision History for the Symmetric Cryptographic Accelerator Hard IP User Guide
1. Introduction x
1.1. Terminology 1.2. IP Overview 1.3. Release Information 1.4. Device Family Support 1.5. Resource Utilization
1.2. IP Overview x
1.2.1. IP Applications
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. AXI-ST Interface 2.4. AXI-Lite Interface
4. Designing with the IP x
4.1. Installing and Licensing IP Cores 4.2. Specifying the IP Parameters and Options 4.3. Generated File Structure 4.4. Symmetric Cryptographic Accelerator Hard IP Flow 4.5. Dynamically Disabling the SM4 Capability 4.6. Error Handling 4.7. Error Reporting 4.8. Resetting the IP 4.9. Channel Definition and Allocation 4.10. Byte Ordering 4.11. AXI-ST Single Packet Mode 4.12. AXI-ST Multiple Packet Mode
4.1. Installing and Licensing IP Cores x
4.1.1. IP Evaluation Mode
4.6. Error Handling x
4.6.1. Steps to Record and Report the Received Errors to the Soft Logic 4.6.2. Detected Error Handling 4.6.3. Key RAM ECC Error Handling
4.6.2. Detected Error Handling x
4.6.2.1. Recovering from a Recoverable Error 4.6.2.2. Recovering from an Internal Error
5. Block Description x
5.1. Reset Sequencer 5.2. AXI-ST Ready Latency 5.3. AXI Adapter 5.4. Integrity Check Value Comparison 5.5. GCM Padding and Depadding
5.3. AXI Adapter x
5.3.1. MAC Packing 5.3.2. Data Last Indicator 5.3.3. Stream and Channel ID Buffering 5.3.4. TKEEP and LAST_SEGMENT Signals Generation 5.3.5. MAC Dropping on Decryption
5.5. GCM Padding and Depadding x
5.5.1. GCM Padding 5.5.2. GCM Depadding
6. Cryptographic IP Data Profiles x
6.1. MAC Security Profile (MACsec) 6.2. IP Security Profile (IPsec) 6.3. Generic GCM Profile (GCM) 6.4. Generic XTS Profile (XTS)
6.1. MAC Security Profile (MACsec) x
6.1.1. MACsec Flow 6.1.2. AXI-ST Interface Using MAC Security (MACsec) Profile Pattern
6.2. IP Security Profile (IPsec) x
6.2.1. AXI-ST Interface Using IP Security (IPsec) Profile Pattern
6.3. Generic GCM Profile (GCM) x
6.3.1. AXI- ST Interface Using Generic GCM Profile Pattern
6.4. Generic XTS Profile (XTS) x
6.4.1. AXI-ST Interface Using Generic XTS Profile Pattern
8. Design Example x
8.1. Functional Description 8.2. Crypto VSIP Top Block Descriptions 8.3. Test Configurations 8.4. Software Requirements 8.5. Simulation Requirements 8.6. Steps to Generate the Design Example 8.7. Running Simulation Tests 8.8. Running Hardware Tests
8.2. Crypto VSIP Top Block Descriptions x
8.2.1. Clock and Reset 8.2.2. Host Interface
8.7. Running Simulation Tests x
8.7.1. Steps to Simulate the Design Example
8.8. Running Hardware Tests x
8.8.1. Supported Boards 8.8.2. Steps to Compile the Design Example for Hardware 8.8.3. Steps to Run the Design Example on Hardware
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP
5. Block Description
6. Cryptographic IP Data Profiles
7. Configuration Registers
8. Design Example
9. Document Revision History for the Symmetric Cryptographic Accelerator Hard IP User Guide

8.8.1. Supported Boards

The example design runs in an Agilex™ 7 FPGA equipped with the In-Line Crypto Accelerator (ICA) hard IP, contained within the Symmetric Cryptographic Accelerator Hard IP. The Agilex™ 7 FPGA must be mounted on a printed circuit board that supplies power, clocks, resets, interface connectors, switches, indicators, and other ancillary components.
Note:

For Quartus® Prime Pro Edition version 22.3, use your own board. In the Symmetric Cryptographic Accelerator Hard IP parameter editor, select User-Designed Board for Targeted Board for Example Design. Support for an Altera® development kit with an FPGA containing the Crypto Hard IP is available in newer releases of the Quartus® Prime Pro Edition software.

For Quartus® Prime Pro Edition version 25.3 and newer, if you specify the AGFD023R24C2E1VC device, the DK-DEV-AGF023FA Agilex™ Development Kit with Integrated Crypto Accelerator option becomes available. Select this development kit to generate a fully-constrained design example.

If you select User-Designed Board, the design example defines two device pins only:

  • i_board_clk—drive this pin with a 100 MHz clock sourced on the board.
  • i_board_rstn—drive this user pin with any input you choose.

In the .qsf, the settings are specified as:

set_location_assignment PIN_FV52 -to i_board_rstn
set_location_assignment PIN_FK46 -to i_board_clk

For the User-Designed Board option, the Quartus® Prime software inserts placeholders for these assignments in the .qsf. Edit the placeholder assignments to match your board design.

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