F-Tile Dynamic Reconfiguration Design Example User Guide

ID 710582
Date 9/26/2022

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Document Table of Contents

1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters

Figure 5. PMA/FEC Direct PHY Multirate Example Design Tab
Table 4.  PMA/FEC Direct PHY Multirate Design Example Parameters
Parameters Value Description
Select Protocol/mode


Select the IP protocol for dynamic reconfiguration.
Select Base Variant



Select the configuration of base variant for dynamic reconfiguration.
Example Design Files Simulation


Simulation option generates the testbench and compilation-only project. Synthesis option generates the hardware design example.
Note: Hardware design example support is not available for 400G-8 base variant.
Generated File Format Verilog


Select the HDL files format. If you select VHDL, you must simulate the testbench with a mixed-language simulator.
Target Development Kit None

Agilex I-Series Transceiver-SoC Development Kit

Target development kit option specifies the target device used to generate the project.