A newer version of this document is available. Customers should click here to go to the newest version.
3.1.2. Ethernet Multirate Hardware Design Example
In the hardware design example, the reset, status, and control signals from packet clients, F-Tile Ethernet Multirate Intel® FPGA IP, and F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP in the example design are connected to In-System Sources and Probes IPs (ISSP). The hardware test scripts open service to the ISSP to read and drive the values. A JTAG host is instantiated to access the Avalon® memory-mapped interfaces.
The hardware design example executes the dynamic reconfiguration transition process, check the DUT IP status, clear the MAC statistics before sending 16 packets, and lastly display the MAC statistics.
Hardware Flow for Design Example:
- For PTP enabled designs using Advance Accuracy Mode (i.e. 25GE-1 with RSFEC and PTP and 400G-8 with RSFEC and PTP), you must generate the routing delay information first before you run the main_script.tcl. For the steps required to generate this routing delay information, refer to Routing Delay Adjustment for Advanced Timestamp Accuracy Mode in F-tile Ethernet Intel FPGA Hard IP User Guide.
- For PTP enabled designs that target the Agilex I-Series Transceiver-SoC Development Kit, the master TOD clock is sourced from U19, OUT1. You must program the OUT1 clock from the default of 166.6Mhz to the required 125Mhz frequency using the development kit's clock controller GUI. For designs which do not use PTP but target the Agilex I-Series Transceiver-SoC Development kit, the default clock settings are sufficient and this step is not required.
- Open System Console and navigate to the hwtest directory.
- Run the script. The script performs the dynamic reconfiguration steps and starts the packet client interface for the different datarates.
- Analyze the results. A successful run displays Test <ftile_eth_dr_test> Passed at System Console.
Did you find the information on this page useful?