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Visible to Intel only — GUID: mam1639667967042
Ixiasoft
2.1.2. CPRI Multirate Hardware Design Example
In the hardware design example, the reset, status, and control signals from packet clients, F-Tile CPRI PHY Multirate Intel® FPGA IP, and F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP in the example design are connected to In-System Sources and Probes IPs (ISSP). The hardware test scripts open service to the ISSP to read and drive the values. A JTAG host is instantiated to access the Avalon® memory-mapped interfaces.
- Enable the packet round-trip measurement.
- Perform the deterministic latency test flow.
- Print the deterministic latency data to det_latency.log file.
- Power up the CPRI PHY Multirate IP DUT based on profile 0 (24G RSFEC).
- Initialize the testbench variables based on power-up profile. The variables are:
- cpri_speed: To indicate the speed of the current profile.
- enable_rsfec: To indicate whether RS-FEC is enabled or disabled for the current profile.
- current_dr_profile: To indicate the ID of the current profile.
- Perform dynamic reconfiguration.
- Check the testbench error flag and determine whether testbench passed or failed. This error flag is set to 1 if there is any error after dynamic reconfiguration traffic tests.
- DR_TRANSITION: Intended dynamic reconfiguration sequence array. The size of this array variable determines the number of dynamic reconfiguration to be performed.
set DR_TRANSITION(0) "10G"
set DR_TRANSITION(1) " 4P9G"
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