F-Tile Dynamic Reconfiguration Design Example User Guide

ID 710582
Date 9/26/2022

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Document Table of Contents

2.1.2. CPRI Multirate Hardware Design Example

Figure 8. CPRI Multirate Hardware Design Example Block Diagram

In the hardware design example, the reset, status, and control signals from packet clients, F-Tile CPRI PHY Multirate Intel® FPGA IP, and F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP in the example design are connected to In-System Sources and Probes IPs (ISSP). The hardware test scripts open service to the ISSP to read and drive the values. A JTAG host is instantiated to access the Avalon® memory-mapped interfaces.

Hardware Flow for Design Example:
  1. Enable the packet round-trip measurement.
    • Perform the deterministic latency test flow.
    • Print the deterministic latency data to det_latency.log file.
  2. Power up the CPRI PHY Multirate IP DUT based on profile 0 (24G RSFEC).
  3. Initialize the testbench variables based on power-up profile. The variables are:
    • cpri_speed: To indicate the speed of the current profile.
    • enable_rsfec: To indicate whether RS-FEC is enabled or disabled for the current profile.
    • current_dr_profile: To indicate the ID of the current profile.
  4. Perform dynamic reconfiguration.
  5. Check the testbench error flag and determine whether testbench passed or failed. This error flag is set to 1 if there is any error after dynamic reconfiguration traffic tests.
For customization, you can modify the DR_TRANSITION array variable in src or parameter file to configure test flow. Profile ID is passed into Dynamic Reconfiguration IP to configure the intended dynamic reconfiguration task.
  • DR_TRANSITION: Intended dynamic reconfiguration sequence array. The size of this array variable determines the number of dynamic reconfiguration to be performed.
For example, you want to achieve this Dynamic Reconfiguration sequence: 24G RS-FEC > 10G > 4.9G. The variables changes are:
set DR_TRANSITION(0)   "10G"
set DR_TRANSITION(1)   " 4P9G"