F-Tile HDMI Intel® FPGA IP Design Example User Guide

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ID 709314
Date 3/17/2023
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices 2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) 3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) 4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) x
2.1. Design Features 2.2. Hardware and Software Requirements 2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.4. Design Parameters 2.5. Design Components 2.6. Design Software Flow 2.7. Clocking Scheme 2.8. Interface Signals 2.9. Hardware Setup 2.10. Simulation Testbench 2.11. Debugging Features
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram x
2.3.1. Creating RX-Only or TX-Only Designs
2.4. Design Parameters x
2.4.1. IP Parameters 2.4.2. HDMI Intel® FPGA IP Design Example Parameters
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.5.1. HDMI TX Components x
2.5.1.1. TX PHY Adapter
2.5.1.1. TX PHY Adapter x
2.5.1.1.1. FRL and TMDS
2.5.2. HDMI RX Components x
2.5.2.1. RX PHY Adapter
2.11. Debugging Features x
2.11.1. Software Debug Message 2.11.2. SCDC Information from Sink Connected to TX 2.11.3. Clock Frequency Measurement
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) x
3.1. Design Features 3.2. Hardware and Software Requirements 3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams 3.4. Design Parameters 3.5. Design Components 3.6. Design Software Flow 3.7. Clocking Scheme 3.8. Interface Signals 3.9. Hardware Setup
3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams x
3.3.1. HDMI 2.1 RX-TX Direct Retransmit Design Block Diagram (Without Video Frame Buffer) 3.3.2. HDMI 2.1 RX-TX Retransmit Design Block Diagram (With Video Frame Buffer)
3.4. Design Parameters x
3.4.1. HDMI RX Direction 3.4.2. HDMI TX Direction
3.6. Design Software Flow x
3.6.1. Configure Redriver Setting 3.6.2. Initialize TX Path 3.6.3. Initialize RX Path 3.6.4. Initialize HDMI TX Register 3.6.5. Wait for RX Path Ready 3.6.6. TX Reconfiguration and Link Training 3.6.7. Set TX Video Clock 3.6.8. Set AXI2CV Configuration 3.6.9. HDMI TX Transmit Video
3.7. Clocking Scheme x
3.7.1. HDMI 2.1 RX-TX Retransmit Design without Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same Clock = ON) 3.7.2. HDMI 2.1 RX-TX Retransmit Design with Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same = OFF) 3.7.3. Clock Details
3.8. Interface Signals x
3.8.1. Platform Design System
3.9. Hardware Setup x
3.9.1. Supporting Additional Video Resolutions
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None)
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full)
4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide

2.5.2. HDMI RX Components

The HDMI RX top components include the RX core top-level components, optional I2C slave and EDID RAM, IOPLL, RX PMA Direct PHY, DCFIFO and 64 bits to 40 bits converter blocks.
Figure 15. HDMI RX Top Components
Table 13.  HDMI RX Top Components
Module Description
HDMI RX Core

The IP receives the serial data from the Transceiver PMA Direct PHY and performs data alignment, channel deskew, TMDS decoding, auxiliary data decoding, video data decoding, audio data decoding, and descrambling.

I2C Slave
I2C is the interface used for Sink Display Data Channel (DDC) and Status and Data Channel (SCDC). The HDMI source uses the DDC to determine the capabilities and characteristics of the sink by reading the Enhanced Extended Display Identification Data (E-EDID) data structure.
  • The 8-bit I2C slave addresses for E-EDID are 0xA0 and 0xA1. The LSB indicates the access type: 1 for read and 0 for write. When an HPD event occurs, the I2C slave responds to E-EDID data by reading from the on-chip RAM.
  • The I2C slave-only controller also supports SCDC for HDMI 2.0 and 2.1 operations. The 9-bit I2C slave address for the SCDC are 0xA8 and 0xA9. When an HPD event occurs, the I2C slave performs write or read transaction to or from SCDC interface of the HDMI RX core.
  • Link training process for Fixed Rate Link (FRL) also happens through I2C interface. During an HPD event or when the source writes a different FRL rate to the FRL Rate register (SCDC registers 0x31 bit[3:0]), the link training process starts.
    Note: This I2C slave-only controller for SCDC is not required if HDMI 2.0 or HDMI 2.1 is not intended.
EDID RAM

The design stores the EDID information using the RAM 1-Port IP. A standard two-wire (clock and data) serial bus protocol (I2C slave-only controller) transfers the CEA-861-D Compliant E-EDID data structure. This EDID RAM stores the E-EDID information.

  • When in TMDS mode, the design supports EDID passthrough from TX to RX. During EDID passthrough, when the TX is connected to the external sink, the Nios® II processor reads the EDID from the external sink and writes to the EDID RAM.
  • When in FRL mode, the Nios® II processor writes the pre-configured EDID for each link rate based on the HDMI_RX_MAX_FRL_RATE parameter in the global.h script.
Use the following HDMI_RX_MAX_FRL_RATE input for the supported FRL rate:
  • 6: 12G 4 Lanes
  • 5: 10G 4 Lanes
  • 4: 8G 4 Lanes
  • 3: 6G 4 Lanes
  • 2: 6G 3 Lanes
  • 1: 3G 3 Lanes
  • 0: No FRL
Output buffer This buffer acts as an interface to interact the I2C interface of the HDMI DDC component.
IOPLL

The HDMI RX uses one IOPLL to generate the FRL clock for the RX core. This reference clock receives the CDR recovered clock.

FRL clock frequency = Data rate per lanes x 4 / (FRL characters per clock x 18)
RX PMA Direct PHY

Hard transceiver block that receives the serial data from an external video source. It deserializes the serial data to parallel data before passing the data to the HDMI RX core. This block runs on PMA Direct for FRL and TMDS modes.

RX CDR has two reference clocks driven by F-tile Reference and System PLL Clock IP. Reference clock 0 connects to a fixed 100 MHz clock. In TMDS mode, RX CDR is reconfigured to select reference clock 1, and in FRL mode, RX CDR is reconfigured to select reference clock 0.

DCFIFO Synchronize data and signals across the System clock and RX clock domains.
F-tile Reference and System PLL Clock IP F-tile Reference and System PLL Clock IP has two reference clocks:
  • Reference clock 0 is connected to a fixed 100 MHz clock for FRL mode
  • Reference clock 1 is connected to TMDS clock channel

Section Content
RX PHY Adapter

Level Two Title