A newer version of this document is available. Customers should click here to go to the newest version.
- 3.7.1. HDMI 2.1 RX-TX Retransmit Design without Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same Clock = ON)
- 3.7.2. HDMI 2.1 RX-TX Retransmit Design with Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same = OFF)
2.5.2. HDMI RX Components
|HDMI RX Core||
The IP receives the serial data from the Transceiver PMA Direct PHY and performs data alignment, channel deskew, TMDS decoding, auxiliary data decoding, video data decoding, audio data decoding, and descrambling.
I2C is the interface used for Sink Display Data Channel (DDC) and Status and Data Channel (SCDC). The HDMI source uses the DDC to determine the capabilities and characteristics of the sink by reading the Enhanced Extended Display Identification Data (E-EDID) data structure.
The design stores the EDID information using the RAM 1-Port IP. A standard two-wire (clock and data) serial bus protocol (I2C slave-only controller) transfers the CEA-861-D Compliant E-EDID data structure. This EDID RAM stores the E-EDID information.
|Output buffer||This buffer acts as an interface to interact the I2C interface of the HDMI DDC component.|
The HDMI RX uses one IOPLL to generate the FRL clock for the RX core. This reference clock receives the CDR recovered clock.
FRL clock frequency = Data rate per lanes x 4 / (FRL characters per clock x 18)
|RX PMA Direct PHY||
Hard transceiver block that receives the serial data from an external video source. It deserializes the serial data to parallel data before passing the data to the HDMI RX core. This block runs on PMA Direct for FRL and TMDS modes.
RX CDR has two reference clocks driven by F-tile Reference and System PLL Clock IP. Reference clock 0 connects to a fixed 100 MHz clock. In TMDS mode, RX CDR is reconfigured to select reference clock 1, and in FRL mode, RX CDR is reconfigured to select reference clock 0.
|DCFIFO||Synchronize data and signals across the System clock and RX clock domains.|
|F-tile Reference and System PLL Clock IP||F-tile Reference and System PLL Clock IP has two reference clocks:
RX PHY Adapter
Did you find the information on this page useful?