F-Tile HDMI Intel® FPGA IP Design Example User Guide

ID 709314
Date 3/17/2023

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3.6.4. Initialize HDMI TX Register

Initialize HDMI TX register based on the HDMI RX configurations. The configuration set based on HDMI RX includes:
  • SCDC FRL rate (SCDC_FRL_CONTROL[4:1] register)
  • HDMI mode (STATUS_CONTROL[5] register)
  • AVI infoframe (AVI_PACKET_DATA* register)
  • Color depth (VIDEO_FORMAT[3:0] register)
For TMDS only:
  • TMDS Bit Clock Ratio[17] (STATUS_CONTROL register)