Visible to Intel only — GUID: ixt1660929740390
Ixiasoft
Visible to Intel only — GUID: ixt1660929740390
Ixiasoft
3.5.2.1. TX Parallel Data Mapping Information for SATA Protocol Mode for Different Configurations
When SATA is selected for one PMA lane, and if you Enable Simplified TX data interface option, the tx_parallel_data bus width is reduced from an 80-bit interface to a 76-bit interface. The formula outlined in Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath to calculate the total tx_parallel_data bus is valid except the interface bus width is now reduced to 76-bit from 80-bit. The upper 4 bits are configured to fgt_tx_pma_elecidle bus signal. There is no change to the rx_parallel_data bus width.
Total tx_parallel_data Bit Width Equation for SATA:
tx_parallel_data[(76*N)-1:0]
fgt_tx_pma_elecidle [(4*N)-1:0]
Where:
- N = Number of PMA lanes value from 1 to 16.
Refer to Variables Defining Bits for the Interfacing Ports in Port and Signal Reference for full variable definitions.
Example 1: Total tx_parallel_data Bit Width with 1 SATA Link (N=1) and 32-bit PMA Width
- tx_parallel_data[75:0]
- fgt_tx_pma_elecidle[3:0]
Example 2: Total tx_parallel_data Bit Width with 2 SATA Links (N=2) and 32-bit PMA Width
- tx_parallel_data[151:0]
- fgt_tx_pma_elecidle[7:0]
PMA Configuration | Bits | TX Parallel Data | RX Parallel Data |
---|---|---|---|
FGT PMA Width = 8, 10, 16, 20, 32 Single Width SATA (One PMA Lane [N=1] with PMA Width ≤ 32) |
75 | Write Enable for TX Core FIFO in Elastic Mode | No change, refer to TX and RX Parallel Data Mapping Information (PMA Lanes, N = 1) with the same PMA configuration. |
[73:71] | TX PMA electrical idle mode:
|
||
35 | TX PMA Interface Data Valid | ||
[D-1]:0 | TX Data | ||
FGT PMA Width = 8, 10, 16, 20, 32 Double Width SATA (One PMA Lane [N=1] with PMA Width ≤ 32) |
75 | Write Enable for TX Core FIFO in Elastic Mode | No change, refer to TX and RX Parallel Data Mapping Information (PMA Lanes, N = 1) with the same PMA configuration. |
[73:71] | TX PMA electrical idle mode:
|
||
[D -1 + 36]:36 | TX Data (Upper Data Bits) | ||
35 | TX PMA Interface Data Valid | ||
[D -1]:0 | TX Data (Lower Data Bits) |
- Set the ports to 4'b1111 to enter electrical idle mode
- Set the ports to 4'b0000 to exit electrical idle mode