F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 1/24/2025
Public
Document Table of Contents

3.14.1.7. Preserving Unused Lanes

FHT PMA supports preservation of unused PMA lanes that you plan to use in the next iteration of your FPGA design.
Write 4'b1111 to cfg_preserve_enable (0xF0030[3:0]) to preserve all the unused lanes in a FHT PMA.
Note: Set this register to zeros for normal operation. This is a common register for all four lanes. LSB is for lane 0 and MSB is for lane 3.

When the FHT PMA (TX or RX) is in reset, it is Bias Temperature Instability (BTI) preserved using an internal clock. When the FHT PMA (TX or RX) is out of reset, and it has an appropriate reference clock source, and rx_ready is asserted, it is BTI preserved.

When the FHT PMA (TX or RX) is out of reset, and does not have an appropriate reference clock source, it is not BTI protected anymore. If you transmit a constant stream of zeros or ones, the FHT PMA's TX is not BTI protected anymore.