Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation

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ID 683870
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Intel FPGA Simulation Basics 3. Siemens EDA QuestaSim* Simulator Support 4. Synopsys VCS* and VCS MX Support 5. Aldec Active-HDL and Riviera-PRO Support 6. Cadence Xcelium* Parallel Simulator Support 7. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive A. Intel® Quartus® Prime Pro Edition User Guides
2. Intel FPGA Simulation Basics x
2.1. Intel FPGA Simulation Essential Elements 2.2. Overview of Simulation Tool Flow 2.3. Simulation Tool Flow 2.4. Supported Simulation Types 2.5. Supported Hardware Description Languages 2.6. Supported Simulators 2.7. Intel FPGA Simulation Basics Revision History
2.2. Overview of Simulation Tool Flow x
2.2.1. Compilation Stage 2.2.2. Elaboration Stage 2.2.3. Simulation Stage
2.3. Simulation Tool Flow x
2.3.1. Specifying Logical Libraries 2.3.2. Compiling Files Into Library Directories 2.3.3. The Intel® Quartus® Prime Simulation Library 2.3.4. Understanding Elaboration 2.3.5. Commands To Configure and Run Simulation 2.3.6. Intel FPGA Simulation Generic Workflow
2.3.1. Specifying Logical Libraries x
2.3.1.1. Why Do We Need Logical Library Names?
2.3.2. Compiling Files Into Library Directories x
2.3.2.1. Inputs to Compilation Commands 2.3.2.2. Order of Files for Compilation Commands 2.3.2.3. Compilation Command Line Options 2.3.2.4. Module Definitions in Library Directories
2.3.3. The Intel® Quartus® Prime Simulation Library x
2.3.3.1. The Intel® Quartus® Prime Simulation Library Compiler 2.3.3.2. Running the Simulation Library Compiler in a Terminal 2.3.3.3. Running the Simulation Library Compiler in the GUI 2.3.3.4. Finding Logical Library Names in Simulation Library Compiler Output
2.3.4. Understanding Elaboration x
2.3.4.1. Elaboration Binding Phase 2.3.4.2. Elaboration Checks 2.3.4.3. Elaboration Options
3. Siemens EDA QuestaSim* Simulator Support x
3.1. Quick Start Example (QuestaSim* with Verilog) 3.2. QuestaSim* Simulator Guidelines 3.3. QuestaSim* Simulation Setup Script Example 3.4. Sourcing QuestaSim* Simulator Setup Scripts 3.5. Unsupported Features 3.6. QuestaSim* Simulator Support Revision History
3.2. QuestaSim* Simulator Guidelines x
3.2.1. Passing Parameter Information from Verilog HDL to VHDL 3.2.2. Viewing Simulation Messages 3.2.3. Generating Signal Activity Data for Power Analysis 3.2.4. Viewing Simulation Waveforms
4. Synopsys VCS* and VCS MX Support x
4.1. Quick Start Example (VCS with Verilog) 4.2. VCS and VCS MX Guidelines 4.3. VCS Simulation Setup Script Example 4.4. Sourcing Synopsys VCS* MX Simulator Setup Scripts 4.5. Sourcing Synopsys VCS* Simulator Setup Scripts 4.6. Synopsys VCS* and VCS MX Support Revision History
5. Aldec Active-HDL and Riviera-PRO Support x
5.1. Quick Start Example (Active-HDL VHDL) 5.2. Aldec Active-HDL and Riviera-PRO Guidelines 5.3. Using Simulation Setup Scripts 5.4. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 5.5. Aldec Active-HDL* and Riviera-PRO * Support Revision History
6. Cadence Xcelium* Parallel Simulator Support x
6.1. Using the Command-Line Interface 6.2. Sourcing Cadence Xcelium* Simulator Setup Scripts 6.3. Sourcing Cadence Incisive* Simulator Setup Scripts 6.4. Cadence Xcelium* Parallel Simulator Support Revision History
1. Answers to Top FAQs
2. Intel FPGA Simulation Basics
3. Siemens EDA QuestaSim* Simulator Support
4. Synopsys VCS* and VCS MX Support
5. Aldec Active-HDL and Riviera-PRO Support
6. Cadence Xcelium* Parallel Simulator Support
7. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Intel® Quartus® Prime Pro Edition User Guides

6.3. Sourcing Cadence Incisive* Simulator Setup Scripts

Follow these steps to incorporate the generated Cadence Incisive* IP simulation scripts into a top-level project simulation script.
  1. The generated simulation script contains the following template lines. Cut and paste these lines into a new file. For example, ncsim.sh. 
    # # Start of template
# # If the copied and modified template file is "ncsim.sh", run it as:
# # ./ncsim.sh
# # 
# # Do the file copy, dev_com and com steps
# source ncsim_setup.sh
# SKIP_ELAB=1
# SKIP_SIM=1
# 
# # Compile the top level module
# ncvlog -sv "$QSYS_SIMDIR/../top.sv"
# 
# # Do the elaboration and sim steps
# # Override the top-level name
# # Override the sim options, so the simulation
# # runs forever (until $finish()). 
# source ncsim_setup.sh
# SKIP_FILE_COPY=1
# SKIP_DEV_COM=1
# SKIP_COM=1
# TOP_LEVEL_NAME=top
# USER_DEFINED_SIM_OPTIONS=""
# # End of template
  2. Delete the first two characters of each line (comment and space): 
    # Start of template
# If the copied and modified template file is "ncsim.sh", run it as:
# ./ncsim.sh
# 
# Do the file copy, dev_com and com steps
source ncsim_setup.sh
SKIP_ELAB=1
SKIP_SIM=1
# Compile the top level module
ncvlog -sv "$QSYS_SIMDIR/../top.sv"
# Do the elaboration and sim steps
# Override the top-level name
# Override the sim options, so the simulation
# runs forever (until $finish()).
source ncsim_setup.sh
SKIP_FILE_COPY=1
SKIP_DEV_COM=1
SKIP_COM=1
TOP_LEVEL_NAME=top
USER_DEFINED_SIM_OPTIONS=""
# End of template
  3. Modify the TOP_LEVEL_NAME and compilation step appropriately, depending on the simulation’s top-level file. For example: 
    TOP_LEVEL_NAME=sim_top \
      ncvlog -sv "$QSYS_SIMDIR/../top.sv"
  4. If necessary, add the QSYS_SIMDIR variable to point to the location of the generated IP simulation files. Specify any other changes that you require to match your design simulation requirements. The scripts offer variables to set compilation or simulation options. Refer to the generated script for details.
  5. Run the resulting top-level script from the generated simulation directory by specifying the path to ncsim.sh.
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