Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation

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ID 683870
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Intel FPGA Simulation Basics 3. Siemens EDA QuestaSim* Simulator Support 4. Synopsys VCS* and VCS MX Support 5. Aldec Active-HDL and Riviera-PRO Support 6. Cadence Xcelium* Parallel Simulator Support 7. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive A. Intel® Quartus® Prime Pro Edition User Guides
2. Intel FPGA Simulation Basics x
2.1. Intel FPGA Simulation Essential Elements 2.2. Overview of Simulation Tool Flow 2.3. Simulation Tool Flow 2.4. Supported Simulation Types 2.5. Supported Hardware Description Languages 2.6. Supported Simulators 2.7. Intel FPGA Simulation Basics Revision History
2.2. Overview of Simulation Tool Flow x
2.2.1. Compilation Stage 2.2.2. Elaboration Stage 2.2.3. Simulation Stage
2.3. Simulation Tool Flow x
2.3.1. Specifying Logical Libraries 2.3.2. Compiling Files Into Library Directories 2.3.3. The Intel® Quartus® Prime Simulation Library 2.3.4. Understanding Elaboration 2.3.5. Commands To Configure and Run Simulation 2.3.6. Intel FPGA Simulation Generic Workflow
2.3.1. Specifying Logical Libraries x
2.3.1.1. Why Do We Need Logical Library Names?
2.3.2. Compiling Files Into Library Directories x
2.3.2.1. Inputs to Compilation Commands 2.3.2.2. Order of Files for Compilation Commands 2.3.2.3. Compilation Command Line Options 2.3.2.4. Module Definitions in Library Directories
2.3.3. The Intel® Quartus® Prime Simulation Library x
2.3.3.1. The Intel® Quartus® Prime Simulation Library Compiler 2.3.3.2. Running the Simulation Library Compiler in a Terminal 2.3.3.3. Running the Simulation Library Compiler in the GUI 2.3.3.4. Finding Logical Library Names in Simulation Library Compiler Output
2.3.4. Understanding Elaboration x
2.3.4.1. Elaboration Binding Phase 2.3.4.2. Elaboration Checks 2.3.4.3. Elaboration Options
3. Siemens EDA QuestaSim* Simulator Support x
3.1. Quick Start Example (QuestaSim* with Verilog) 3.2. QuestaSim* Simulator Guidelines 3.3. QuestaSim* Simulation Setup Script Example 3.4. Sourcing QuestaSim* Simulator Setup Scripts 3.5. Unsupported Features 3.6. QuestaSim* Simulator Support Revision History
3.2. QuestaSim* Simulator Guidelines x
3.2.1. Passing Parameter Information from Verilog HDL to VHDL 3.2.2. Viewing Simulation Messages 3.2.3. Generating Signal Activity Data for Power Analysis 3.2.4. Viewing Simulation Waveforms
4. Synopsys VCS* and VCS MX Support x
4.1. Quick Start Example (VCS with Verilog) 4.2. VCS and VCS MX Guidelines 4.3. VCS Simulation Setup Script Example 4.4. Sourcing Synopsys VCS* MX Simulator Setup Scripts 4.5. Sourcing Synopsys VCS* Simulator Setup Scripts 4.6. Synopsys VCS* and VCS MX Support Revision History
5. Aldec Active-HDL and Riviera-PRO Support x
5.1. Quick Start Example (Active-HDL VHDL) 5.2. Aldec Active-HDL and Riviera-PRO Guidelines 5.3. Using Simulation Setup Scripts 5.4. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 5.5. Aldec Active-HDL* and Riviera-PRO * Support Revision History
6. Cadence Xcelium* Parallel Simulator Support x
6.1. Using the Command-Line Interface 6.2. Sourcing Cadence Xcelium* Simulator Setup Scripts 6.3. Sourcing Cadence Incisive* Simulator Setup Scripts 6.4. Cadence Xcelium* Parallel Simulator Support Revision History
1. Answers to Top FAQs
2. Intel FPGA Simulation Basics
3. Siemens EDA QuestaSim* Simulator Support
4. Synopsys VCS* and VCS MX Support
5. Aldec Active-HDL and Riviera-PRO Support
6. Cadence Xcelium* Parallel Simulator Support
7. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Intel® Quartus® Prime Pro Edition User Guides

3.6. QuestaSim* Simulator Support Revision History

Document Version Intel® Quartus® Prime Version Changes
2023.10.02 23.3
  • Updated chapter to reflect end of support for ModelSim and relocation of Questa* Intel® FPGA Edition information to new Questa* Intel® FPGA Edition Simulation User Guide.
  • Removed obsolete Generating Standard Delay Output for Power Analysis topic. Generation of SDO files is no longer supported in the Intel® Quartus® Prime Pro Edition software.
2022.04.13 22.1
  • Revised name of Questa* Intel® FPGA Edition and QuestaSim for latest guidelines throughout.
2021.10.04 21.3
  • Added support for Questa* Intel® FPGA Edition simulator.
  • Removed support for ModelSim - Intel FPGA Edition simulator.
  • Updated directory names in Using Questa* Intel® FPGA Edition Precompiled Libraries topic.
  • Removed note about Maintain Hierarchy limit in Viewing Simulation Messages topic.
2021.03.29 21.1 Updated Generating Signal Activity Data for Power Analysis topic for latest behavior.
2019.06.19 19.1.0
  • Added footnote about ModelSim Remote Desktop limits to "Unsupported Features" topic.
2019.04.01 19.1.0
  • Described new support for generation of SDO for use in power analysis.
2017.11.06 17.1.0
  • Changed title to ModelSim - Intel FPGA Edition, ModelSim* , and QuestaSim Support*
  • Removed Simulating Transport Delays and Disabling Timing Violations on Registers topics. Intel® Quartus® Prime Pro Edition does not support timing simulation.
  • Added Simulation Library Compiler details and another step to Quick Start Example

Date

Version

Changes

2017.11.06 17.1.0
  • Changed title to ModelSim - Intel FPGA Edition, ModelSim* , and QuestaSim Support*
  • Stated no support for Intel® Arria® 10 timing simulation in Simulating Transport Delays and Disabling Timing Violations on Registers topics.
  • Added Simulation Library Compiler details and another step to Quick Start Example
2017.05.08 17.0.0
  • Removed note about unsupported NativeLink gate level simulation.
2016.10.31 16.1.0
  • Implemented Intel rebranding.
  • Corrected load design syntax error.
2016.05.02 16.0.0
  • Removed support for NativeLink simulation in Pro Edition
  • Added note about avoiding ModelSim - Intel FPGA Edition instance limitations.
2016.05.02 16.0.0
  • Noted limitations of NativeLink simulation.
  • Added note about avoiding ModelSim - Intel FPGA Edition instance limitations.
2015.11.02 15.1.0 Changed instances of Quartus II to Quartus Prime.
2015.11.02 15.1.0 Changed instances of Quartus II to Quartus Prime.

2015.05.04

15.0.0
  • Added mixed language simulation support in the ModelSim - Intel FPGA Edition software.

2014.06.30

14.0.0
  • Replaced MegaWizard Plug-In Manager information with IP Catalog.

November 2012

12.1.0

  • Relocated general simulation information to Simulating Altera Designs.

June 2012

12.0.0

  • Removed survey link.

November 2011

11.0.1

  • Changed to new document template.
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