OPAE Intel FPGA Linux Device Driver Architecture Guide

ID 683857
Date 10/02/2017
Public
Document Table of Contents

1.1.2. Port

A Port represents the interface between the static FPGA fabric (the “FPGA Interface Manager (FIM)”) and a partially reconfigurable region containing an Accelerator Function (AF). The Port controls the communication from software to the accelerator and exposes features such as reset and debug.

A PCIe device may have several Ports, and each Port can be exposed through a VF by assigning it using the FPGA_FME_PORT_ASSIGN ioctl on the FME device.