OPAE Intel FPGA Linux Device Driver Architecture Guide

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ID 683857
Date 10/02/2017
Public
Document Table of Contents
Document Table of Contents x
1. OPAE Intel® FPGA Linux Device Driver Architecture
1. OPAE Intel® FPGA Linux Device Driver Architecture x
1.1. Hardware Architecture 1.2. sysfs Files 1.3. Revision History
1.1. Hardware Architecture x
1.1.1. FPGA Management Engine (FME) 1.1.2. Port 1.1.3. Accelerator Function (AF) Unit 1.1.4. Partial Reconfiguration 1.1.5. FPGA Virtualization 1.1.6. Driver Organization 1.1.7. Application FPGA Device Enumeration 1.1.8. PCIe Driver Enumeration 1.1.9. FME Platform Device Initialization 1.1.10. Port Platform Device Initialization 1.1.11. FME IOCTLs 1.1.12. Port IOCTLs
1.1.6. Driver Organization x
1.1.6.1. PCIe Module Device Driver 1.1.6.2. PCIe Module Device Driver Functions 1.1.6.3. FME Platform Module Device Driver 1.1.6.4. FME Platform Module Device Driver Functions 1.1.6.5. Port Platform Module Device Driver 1.1.6.6. Port Platform Module Device Driver Functions
1.1.8. PCIe Driver Enumeration x
1.1.8.1. Enumeration Data Structures 1.1.8.2. Enumeration Flow
1.1.9. FME Platform Device Initialization x
1.1.9.1. FME Platform Device Data Structures 1.1.9.2. FME Platform Device Initialization Flow
1.1.10. Port Platform Device Initialization x
1.1.10.1. Port Platform Device Data Structures 1.1.10.2. Port Platform Device Initialization Flow
1.2. sysfs Files x
1.2.1. FME Header sysfs files 1.2.2. FME Thermal Management sysfs files 1.2.3. FME Power Management sysfs files 1.2.4. FME Global Error sysfs files 1.2.5. FME Partial Reconfiguration sysfs files 1.2.6. FME Global Performance sysfs files 1.2.7. Port Header sysfs files 1.2.8. Port AFU Header sysfs files 1.2.9. Port Error sysfs files
1. OPAE Intel® FPGA Linux Device Driver Architecture

1.1.12. Port IOCTLs

IOCTLs that are called on an open file descriptor for /dev/intel-fpga-port.k

FPGA_GET_API_VERSION—return the current version as an integer, starting from 0.

FPGA_CHECK_EXTENSION—not currently supported.

FPGA_PORT_GET_INFO—arg is a pointer to a: 

struct fpga_port_info { 
	__u32 argsz; // in: sizeof(struct fpga_port_info) 
	__u32 flags; // out: returns 0 
	__u32 num_regions; // out: number of MMIO regions, 2 (1 for AFU and 1 for STP) 
	__u32 num_umsgs; // out: number of UMsg's supported by the hardware 
};
FPGA_PORT_GET_REGION_INFO—arg is a pointer to a: 

struct fpga_port_region_info { 
	__u32 argsz; // in: sizeof(struct fpga_port_region_info) 
	__u32 flags; // out: (bitmask) { FPGA_REGION_READ, FPGA_REGION_WRITE, FPGA_REGION_MMAP }
	__u32 index; // in: FPGA_PORT_INDEX_UAFU or FPGA_PORT_INDEX_STP 
	__u32 padding; // in: must be 0 
	__u64 size; // out: size of MMIO region in bytes 
	__u64 offset; // out: offset of MMIO region from start of device fd 
};
FPGA_PORT_DMA_MAP—arg is a pointer to a: 

struct fpga_port_dma_map { 
	__u32 argsz; // in: sizeof(struct fpga_port_dma_map) 
	__u32 flags; // in: must be 0 __u64 user_addr; // in: process virtual address. Must be page aligned. 
	__u64 length; // in: length of mapping in bytes. Must be a multiple of page size. 
	__u64 iova; // out: IO virtual address };
FPGA_PORT_DMA_UNMAP—arg is a pointer to a: 

struct fpga_port_dma_unmap { 
	__u32 argsz; // in: sizeof(struct fpga_port_dma_unmap) 
	__u32 flags; // in: must be 0 
	__u64 iova; // in: IO virtual address returned by a previous FPGA_PORT_DMA_MAP };

FPGA_PORT_RESET—arg must be NULL.

FPGA_PORT_UMSG_ENABLE—arg must be NULL.

FPGA_PORT_UMSG_DISABLE—args must be NULL.

FPGA_PORT_UMSG_SET_MODE—arg is a pointer to a: 

struct fpga_port_umsg_cfg { 
	__u32 argsz; // in: sizeof(struct fpga_port_umsg_cfg) 
	__u32 flags; // in: must be 0 
	__u32 hint_bitmap; // in: UMsg hint mode bitmap. Signifies which UMsg's are enabled. 
};
FPGA_PORT_UMSG_SET_BASE_ADDR—
  • UMsg must be disabled prior to issuing this ioctl.
  • The iova field must be for a buffer large enough for all UMsg’s (num_umsgs * PAGE_SIZE).
    • The buffer is marked as “in use” by the driver’s buffer management.
    • If iova is NULL, any previous region is unmarked as “in use”.
  • arg is a pointer to a:
    
struct fpga_port_umsg_base_addr { 
	__u32 argsz; // in: sizeof(struct fpga_port_umsg_base_addr) 
	__u32 flags; // in: must be 0 
	__u64 iova; // in: IO virtual address from FPGA_PORT_DMA_MAP. };
Note: To clear the port errors, you have to write the exact bitmask of the current errors, for example: cat errors > clear
Note: UMsg is only supported through Acceleration Stack for Intel® Xeon® Processor with Integrated FPGA.
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