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1.1.1. FPGA Management Engine (FME)
1.1.2. Port
1.1.3. Accelerator Function (AF) Unit
1.1.4. Partial Reconfiguration
1.1.5. FPGA Virtualization
1.1.6. Driver Organization
1.1.7. Application FPGA Device Enumeration
1.1.8. PCIe Driver Enumeration
1.1.9. FME Platform Device Initialization
1.1.10. Port Platform Device Initialization
1.1.11. FME IOCTLs
1.1.12. Port IOCTLs
1.2.1. FME Header sysfs files
1.2.2. FME Thermal Management sysfs files
1.2.3. FME Power Management sysfs files
1.2.4. FME Global Error sysfs files
1.2.5. FME Partial Reconfiguration sysfs files
1.2.6. FME Global Performance sysfs files
1.2.7. Port Header sysfs files
1.2.8. Port AFU Header sysfs files
1.2.9. Port Error sysfs files
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1.1.10. Port Platform Device Initialization
This section gives an overview of the code flow for port device initialization performed by intel-fpga-afu.ko. The main data structures and functions are highlighted. This section is best followed when viewing the accompanying source code (afu.c).