AN 835: PAM4 Signaling Fundamentals

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ID 683852
Date 3/12/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. CEI-56G-MR Transmitter 3. CEI-56G-MR-PAM4 Interface Details 4. CEI-56G-MR-PAM4 Receiver 5. PAM4 Link Case Study 6. Medium Reach (MR) PAM4 System Design Study 7. Glossary and Acronyms 8. References 9. Document Revision History for AN 835: PAM4 Signaling Fundamentals
1. Introduction x
1.1. NRZ Fundamentals 1.2. Standards Using PAM4 Coding Scheme 1.3. CEI-56G Interconnect Reaches and Application Distances
1.3. CEI-56G Interconnect Reaches and Application Distances x
1.3.1. VSR (Very Short Reach) Chip-to-Module 1.3.2. MR (Mid-Range Reach) - Chip to Chip Within a PCBA 1.3.3. LR (Long Reach) - Chip to Chip Across a Backplane/Midplane or a Cable
2. CEI-56G-MR Transmitter x
2.1. Naming Conventions 2.2. Eye Height (EH6) and Eye Width (EW6) 2.3. Eye Linearity 2.4. Electrical Characteristics 2.5. PAM4 Jitter Methodology 2.6. TX Pre-Emphasis Method
2.4. Electrical Characteristics x
2.4.1. Transmitter Characteristics 2.4.2. Transmitter Return Loss 2.4.3. Transmitter Linearity (RLM) 2.4.4. Signal-to-Noise-and-Distortion Ratio (SNDR)
3. CEI-56G-MR-PAM4 Interface Details x
3.1. COM Introduction 3.2. Normative Channel Specification COM 3.3. Informative Channel Insertion Loss 3.4. Informative Channel Return Loss
3.1. COM Introduction x
3.1.1. Backplane Measurements
4. CEI-56G-MR-PAM4 Receiver x
4.1. Challenges in Analyzing PAM4 Signals 4.2. PAM4 Receiver Architecture 4.3. Equalization Technique 4.4. CEI-56G-MR-PAM4 Receiver Details
4.2. PAM4 Receiver Architecture x
4.2.1. Analog vs. Digital Receiver 4.2.2. Slicer 4.2.3. Clock and Data Recovery (CDR)
4.4. CEI-56G-MR-PAM4 Receiver Details x
4.4.1. Electrical Characteristics 4.4.2. Receiver Input Return Loss 4.4.3. Receiver Interference Tolerance 4.4.4. Receiver Jitter Tolerance
5. PAM4 Link Case Study x
5.1. OIF_Stressed 5.2. OIF_Compliant
5.1. OIF_Stressed x
5.1.1. Channel Characteristics 5.1.2. OIF_Stressed PAM4 Link Simulation with the Advanced Link Analyzer
5.2. OIF_Compliant x
5.2.1. Channel Characteristics 5.2.2. OIF_Compliant PAM4 Link Simulation with the Advanced Link Analyzer
6. Medium Reach (MR) PAM4 System Design Study x
6.1. System Power 6.2. System Cost 6.3. Board Space 6.4. Conclusion
1. Introduction
2. CEI-56G-MR Transmitter
3. CEI-56G-MR-PAM4 Interface Details
4. CEI-56G-MR-PAM4 Receiver
5. PAM4 Link Case Study
6. Medium Reach (MR) PAM4 System Design Study
7. Glossary and Acronyms
8. References
9. Document Revision History for AN 835: PAM4 Signaling Fundamentals

2.6. TX Pre-Emphasis Method

When signals travel through a lossy backplane, signal transitions can expand to adjacent intervals. This effect is known as Inter-Symbol Interference (ISI). The purpose of TX pre-emphasis is to apply delay and inversion to the signal and add it back to the original signal with the proper weight, thereby compensating for ISI from the nearby data symbol.

The transmitter equalization requirements for each CEI standard are defined in their respective COM specifications. Refer to CEI-56G-MR-PAM4 Interface Details for more information about transmitter equalization requirements. These are the minimum expected pre-emphasis requirements. For an MR channel, there are only three taps:

  • Main cursor
  • Pre-cursor
  • Post-cursor
Table 7.  MR COM Specifications
Parameter Symbol Value Units
Signaling rate fb 18 - 29 Gsym/s
Maximum start frequency fmin 0.05 GHz
Maximum frequency step f 0.01 GHz
Device package model

Single-ended device capacitance

Transmission line length, Test 1

Transmission line length, Test 2

Transmission line characteristic impedance

Single-ended package capacitance at package-to-board interface

Cd

zp

zp

ZC

Cp

160

12

30

85

110

fF

mm

mm

Ω

fF
Single-ended reference resistance R0 50 Ω
Single-ended termination resistance Rd 55 Ω
Receiver 3 dB bandwidth fr 0.75 x fb  
Transmitter equalizer, minimum cursor c(0) 0.60 -
Transmitter equalizer, pre-cursor coefficient

Minimum value

Maximum value

Step size

 c(-1)

-0.15

0

0.05

-

-

-
Transmitter equalizer, post-cursor coefficient

Minimum value

Maximum value

Step size

 c(1)

-0.25

0

0.05

-

-

-
Continuous time filter, DC gain

Minimum value

Maximum value

Step size

 gDC

-15

0

1

dB

dB

dB
Continuous time filter, DC gain2

Minimum value

Maximum value

Step size

 gDC2

-5

0

1

dB

dB

dB
Continuous time filter, zero frequencies fz

fz2

fb/2.5

fb/40

GHz

GHz
Continuous time filter, pole frequencies fp1

fp2

fp3

fb/2.5

fb/40

fb

GHz

GHz
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