AN 835: PAM4 Signaling Fundamentals

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ID 683852
Date 3/12/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. CEI-56G-MR Transmitter 3. CEI-56G-MR-PAM4 Interface Details 4. CEI-56G-MR-PAM4 Receiver 5. PAM4 Link Case Study 6. Medium Reach (MR) PAM4 System Design Study 7. Glossary and Acronyms 8. References 9. Document Revision History for AN 835: PAM4 Signaling Fundamentals
1. Introduction x
1.1. NRZ Fundamentals 1.2. Standards Using PAM4 Coding Scheme 1.3. CEI-56G Interconnect Reaches and Application Distances
1.3. CEI-56G Interconnect Reaches and Application Distances x
1.3.1. VSR (Very Short Reach) Chip-to-Module 1.3.2. MR (Mid-Range Reach) - Chip to Chip Within a PCBA 1.3.3. LR (Long Reach) - Chip to Chip Across a Backplane/Midplane or a Cable
2. CEI-56G-MR Transmitter x
2.1. Naming Conventions 2.2. Eye Height (EH6) and Eye Width (EW6) 2.3. Eye Linearity 2.4. Electrical Characteristics 2.5. PAM4 Jitter Methodology 2.6. TX Pre-Emphasis Method
2.4. Electrical Characteristics x
2.4.1. Transmitter Characteristics 2.4.2. Transmitter Return Loss 2.4.3. Transmitter Linearity (RLM) 2.4.4. Signal-to-Noise-and-Distortion Ratio (SNDR)
3. CEI-56G-MR-PAM4 Interface Details x
3.1. COM Introduction 3.2. Normative Channel Specification COM 3.3. Informative Channel Insertion Loss 3.4. Informative Channel Return Loss
3.1. COM Introduction x
3.1.1. Backplane Measurements
4. CEI-56G-MR-PAM4 Receiver x
4.1. Challenges in Analyzing PAM4 Signals 4.2. PAM4 Receiver Architecture 4.3. Equalization Technique 4.4. CEI-56G-MR-PAM4 Receiver Details
4.2. PAM4 Receiver Architecture x
4.2.1. Analog vs. Digital Receiver 4.2.2. Slicer 4.2.3. Clock and Data Recovery (CDR)
4.4. CEI-56G-MR-PAM4 Receiver Details x
4.4.1. Electrical Characteristics 4.4.2. Receiver Input Return Loss 4.4.3. Receiver Interference Tolerance 4.4.4. Receiver Jitter Tolerance
5. PAM4 Link Case Study x
5.1. OIF_Stressed 5.2. OIF_Compliant
5.1. OIF_Stressed x
5.1.1. Channel Characteristics 5.1.2. OIF_Stressed PAM4 Link Simulation with the Advanced Link Analyzer
5.2. OIF_Compliant x
5.2.1. Channel Characteristics 5.2.2. OIF_Compliant PAM4 Link Simulation with the Advanced Link Analyzer
6. Medium Reach (MR) PAM4 System Design Study x
6.1. System Power 6.2. System Cost 6.3. Board Space 6.4. Conclusion
1. Introduction
2. CEI-56G-MR Transmitter
3. CEI-56G-MR-PAM4 Interface Details
4. CEI-56G-MR-PAM4 Receiver
5. PAM4 Link Case Study
6. Medium Reach (MR) PAM4 System Design Study
7. Glossary and Acronyms
8. References
9. Document Revision History for AN 835: PAM4 Signaling Fundamentals

1.3.3. LR (Long Reach) - Chip to Chip Across a Backplane/Midplane or a Cable

Figure 8. LR Interconnect

This interface communicates between two cards across a backplane or midplane within a chassis and is less than 1 meter with up to two connectors. KP-FEC may be a requirement to meet the BER.

Table 2.  Summary of CEI 56G Different Reaches and Distances
Parameter Ultra Short Reach (USR) Extra Short Reach (XSR) VSR MR LR
Reach 2.5D/3D Chip- to-optics Engine Chip- to-module Chip-to-chip Chip-to-chip over a backplane
Data Rate (Gbps) 19.6-58 39.2-58 39.2-58 36-58 36-58
BER (pre-FEC) 1E-15 1E-15 1E-6 1E-6 1E-4
Distance 10 mm (~0.4") 50 mm (~2") 150 mm (~6") 500 mm (~20") 1000 mm (~40")
Interconnect MCM PCB+0 connector PCB+1 connector PCB+1 connector PCB+2 connectors
Insertion Loss (dB) 2@28 GHz (NRZ) 4@14 GHz (PAM4) 10@14 GHz (PAM4) 20@14 GHz (PAM4) 30@14 GHz (PAM4)
Modulation NRZ PAM4 or NRZ PAM4 or NRZ PAM4 or NRZ PAM4 or ENRZ
FEC No No Yes/No Yes/No Yes/No
Table 3.  Summary of Ethernet 50G/Lane Standards
Reach 400GBE (802.3bs) 200GBE (802.3bs, .cd) 100GBE (802.3cd) 50GBE (802.3cd)
Chip-to-chip (C2C) and Chip-to-module (C2M) 400GAUI-8 200GAUI-4 — —
Backplane (BP) — 200GBASE-KR4 100GBASE-KR2 50GBASE-KR
Copper Cable (CC) — 200GBASE-CR4 100GBASE-CR2 50GBASE-CR
Level Two Title