AN 953: Partially Reconfiguring a Design: on an Intel® Agilex® F-Series FPGA Development Board

Download PDF
ID 683849
Date 7/23/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
Partially Reconfiguring a Design on Intel® Agilex® F-Series FPGA Development Board
Partially Reconfiguring a Design on Intel® Agilex® F-Series FPGA Development Board x
Reference Design Overview Reference Design Requirements Reference Design Files Reference Design Walkthrough Document Revision History for AN 953: Partially Reconfiguring a Design on Intel® Agilex® F-Series FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Defining Personas Step 5: Creating Revisions Step 6: Compiling the Base Revision Step 7: Preparing PR Implementation Revisions Step 8: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 5: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 8: Programming the Board x
Troubleshooting PR Programming Errors
Partially Reconfiguring a Design on Intel® Agilex® F-Series FPGA Development Board

Step 1: Getting Started

To copy the reference design files to your working environment and compile the blinking_led flat design:
  1. Create a directory in your working environment, agilex_pcie_devkit_blinking_led_pr.
  2. Copy the downloaded tutorials/agilex_pcie_devkit_blinking_led/flat sub-folder to the directory, agilex_pcie_devkit_blinking_led_pr.
  3. In the Intel® Quartus® Prime Pro Edition software, click File > Open Project and select blinking_led.qpf.
  4. To elaborate the hierarchy of the flat design, click Processing > Start > Start Analysis & Synthesis. Alternatively, at the command-line, run the following command:
    quartus_syn blinking_led -c blinking_led
Level Two Title