Partially Reconfiguring a Design on Intel® Agilex® F-Series FPGA Development Board
|Intel® Quartus® Prime Design Suite 21.1|
The partial reconfiguration (PR) feature allows you to reconfigure a portion of the FPGA dynamically, while the remaining FPGA design continues to function. You can create multiple personas for a particular region in your design that do not impact operation in areas outside this region. This methodology is effective in systems where multiple functions time-share the same FPGA device resources. The current version of the Intel® Quartus® Prime Pro Edition software introduces a new and simplified compilation flow for partial reconfiguration.
- Allows run-time design reconfiguration
- Increases scalability of the design
- Reduces system down-time
- Supports dynamic time-multiplexing functions in the design
- Lowers cost and power consumption through efficient use of board space
This tutorial uses the Intel® Agilex® F-Series FPGA development board on the bench, outside of the PCIe* slot in your workstation.
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