AN 953: Partially Reconfiguring a Design: on an Intel® Agilex® F-Series FPGA Development Board

ID 683849
Date 7/23/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Give Feedback

Step 4: Defining Personas

This reference design defines three separate personas for the single PR partition. To define and include the personas in your project:

  1. Create three SystemVerilog files, blinking_led.sv, blinking_led_slow.sv, and blinking_led_empty.sv in your working directory for the three personas.
    Table 2.  Reference Design Personas
    File Name Description Code
    blinking_led.sv Default persona with same design as the flat implementation
    `timescale 1 ps / 1 ps
    `default_nettype none
    
    
    module blinking_led (
        // clock
        input wire clock,
        input wire [31:0] counter,
    
        // Control signals for the LEDs
        output wire led_two_on,
        output wire led_three_on
    );
    
        localparam COUNTER_TAP = 23;
    
        reg led_two_on_r;
        reg led_three_on_r;
      
        assign led_two_on = led_two_on_r;
        assign led_three_on = led_three_on_r;
    
        always_ff @(posedge clock) 
        begin
            led_two_on_r <= counter[COUNTER_TAP];
            led_three_on_r <= counter[COUNTER_TAP];
        end
    
    endmodule
    blinking_led_slow.sv LEDs blink slower
    `timescale 1 ps / 1 ps
    `default_nettype none
    
    module blinking_led_slow (
        // clock
        input wire clock,
        input wire [31:0] counter,
    
        // Control signals for the LEDs
        output wire led_two_on,
        output wire led_three_on
    );
    
        localparam COUNTER_TAP = 27;
    
        reg led_two_on_r;
        reg led_three_on_r;
     
        assign led_two_on = led_two_on_r;
        assign led_three_on = led_three_on_r;
    
        always_ff @(posedge clock) 
        begin
           led_two_on_r <= counter[COUNTER_TAP];
           led_three_on_r <= counter[COUNTER_TAP];
        end
    
    endmodule
    blinking_led_empty.sv LEDs stay ON
    `timescale 1 ps / 1 ps
    `default_nettype none
    
    module blinking_led_empty(
        // clock
        input wire clock,
        input wire [31:0] counter,
    
        // Control signals for the LEDs
        output wire led_two_on,
        output wire led_three_on
    );
    
        // LED is active low 
        assign led_two_on = 1'b0;
        assign led_three_on = 1'b0;
    
    endmodule
Note:
  • blinking_led.sv is already available as part of the files you copy from the flat/ sub-directory. You can simply reuse this file.
  • If you create the SystemVerilog files from the Intel® Quartus® Prime Text Editor, disable the Add file to current project option, when saving the files.