AN 953: Partially Reconfiguring a Design: on an Intel® Agilex® F-Series FPGA Development Board

ID 683849
Date 7/23/2021

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Reference Design Overview

This reference design used in this tutorial consists of one 32-bit counter. At the board level, the design connects the clock to a 50 MHz source and connects the output to four LEDs on the board. Selecting the output from the counter bits in a specific sequence causes the LEDs to blink at a specific frequency.
Figure 1. Flat Reference Design without PR Partitioning

In this tutorial, the partial reconfiguration flow updates the function of u_blinking_led.